公开(公告)号：JP2000286336A

公开(公告)日：2000-10-13

申请号：JP2000004807

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  WOLF THOMAS MICHAEL ,  YEN ALLEN

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To form an integrated circuit of a stacked structure having a large cross-sectional shape by forming a through hole or a contact of a through conductor under a hard mask and a second photoresist layer, using both the hard mask and the second photoresist layer as a mask. SOLUTION: In a dielectric layer 1, two conductors 3, 5 are formed. A silicon nitride hard mask 7 is formed above these conductors 3, 5 and a first photoresist layer is formed on the hard mask 7. Then, the first photoresist layer is removed and a second photoresist layer 15 is formed. The second photoresist layer 15 is patterned to form second slender openings 17, 19 stretching across a trench 13. Then, third square openings 18, 20 are formed from the bottom of the trench 13 up to the top of the conductors 3, 5. By a metallization process for filling the openings 18, 20 and a following flattening process for the second photoresist layer 15 and the hard mask 7, a desired square contact like the through conductors is formed.

公开(公告)号：JP2001102377A

公开(公告)日：2001-04-13

申请号：JP2000248125

申请日：2000-08-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GERARD W GIBSON ,  STEVEN ALAN LITTLE ,  MARY DORUMONDO ROBBY ,  DANIEL JOSEPH BITTOKABAJI ,  WOLF THOMAS MICHAEL

IPC: H01L21/768 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L27/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a dielectric layer of low permittivity in an integrated circuit. SOLUTION: A step, where a dielectric layer of multi-layer structure is formed on a substrate, is provided, with the dielectric layer of multilayer structure comprising a structure-body layer and a dielectric layer of low pesmittivity.

公开(公告)号：JP2001110901A

公开(公告)日：2001-04-20

申请号：JP2000248124

申请日：2000-08-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GERARD W GIBSON ,  STEVEN ALAN LITTLE ,  MARY DORUMONDO ROBBY ,  DANIEL JOSEPH BITTOKABAJI ,  WOLF THOMAS MICHAEL

IPC: H01L27/00 ,  H01L21/316 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method of providing a dielectric layer of low dielectric constant on an integrated circuit. SOLUTION: This method comprises a step where a dielectric layer of multilayered structure is formed on a substrate, and the dielectric layer of multilayered structure is composed of a structure layer and a dielectric layer of low dielectric constant.

公开(公告)号：GB2358734A

公开(公告)日：2001-08-01

申请号：GB0019969

申请日：2000-08-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GIBSON JR GERALD W ,  LYTLE STEVEN ALAN ,  ROBY MARY DRUMMOND ,  VITKAVAGE DANIEL JOSEPH ,  WOLF THOMAS MICHAEL

IPC: H01L27/00 ,  H01L21/316 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04

Abstract: A process for fabricating integrated circuit comprising dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100) is disclosed. The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO 2 ) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

公开(公告)号：GB2358733A

公开(公告)日：2001-08-01

申请号：GB0019968

申请日：2000-08-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GIBSON JR GERALD W ,  LYTLE STEVEN ALAN ,  ROBY MARY DRUMMOND ,  VITKAVAGE DANIEL JOSEPH ,  WOLF THOMAS MICHAEL

IPC: H01L21/768 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L27/00

Abstract: An integrated circuit comprises dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100). The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO 2 ) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

公开(公告)号：GB2346009B

公开(公告)日：2002-03-20

申请号：GB0000740

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  WOLF THOMAS MICHAEL ,  YEN ALLEN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/538

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

公开(公告)号：GB2346009A

公开(公告)日：2000-07-26

申请号：GB0000740

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  WOLF THOMAS MICHAEL ,  YEN ALLEN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/538

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer 1 over a conductive material, 3, 5 depositing a hardmask 7 over the dielectric layer 1 applying a first photoresist 9 over the hardmask 7 and photodefining at least one elongated opening 11 etching the hard mask and partially etching the dielectric 1 to form a trench 13 having a bottom, stripping the photoresist, 9 applying a second photoresist 15 and photodefining a slit 14, 19 across the trench, 13 selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Preferably a connection to the conductive materials 3, 5 is formed and integrated circuits made thereby. Preferably, one of the connections has a quadrilateral cross-section of less than 0.5 micron.