公开(公告)号：JPH0951045A

公开(公告)日：1997-02-18

申请号：JP26697295

申请日：1995-10-16

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAWADA SHIGEKI ,  FURUTA KOJI

IPC: H01L21/8249 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To optimize the operational characteristics of every element independently, lower the emitter resistance value by preventing leakage between emitter bases, and to improve the performance of a bipolar transistor, in a semiconductor integrated circuit device wherein a bipolar transistor and MOS transistors are integrated on the same semiconductor substrate. SOLUTION: A bipolar transistor 1 and both MOS transistors 2 and 3 are integrated on a P-type semiconductor substarte. An oxide film 20A for base extraction electrode side part, a silicon nitride film 21A for base extraction electrode side, and polycrystalline silicon films 22A and 22B for base extraction electrode side are formed in the transistor 1, and oxide films 20C and 20D for gate electrode side part, silicon nitride films 21C and 21D for gate electrode side, and insulation side walls 29A and 29B for gate electrode are formed in the transistors 2 and 3.

公开(公告)号：JPS62118528A

公开(公告)日：1987-05-29

申请号：JP25897485

申请日：1985-11-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI ,  NARAOKA HIROKI

IPC: H01L21/304 ,  H01L21/316

Abstract: PURPOSE:To enable even drying up process to be performed while cutting water film evenly from the end of a wafer by a method wherein, in the cleaning process before sir-knife drying process, an oxide film is formed by chemical processing on an exposed substrate surface to be etched while leaving the oxide film. CONSTITUTION:When an MOS capacitor is formed, a LOCOS (SiO2) separating the capacitor and a pattern on an exposed Si substrate surface to be a capacitor coexist together on one main surface of a wafer. This wafer is cleaned up for the minutes in a cleaning solution with mixing ratio of e.g. NH4OH:H2O2:H2 O=1:2:7. An oxide film around 1mum thick is formed on Si by this cleaning process. After sufficient washing, the oxide film is immersed in a solution with mixing ratio of e.g. H2O:HF=500:1 to be etched by around 0.5mum leaving it by around 0.5nm. After sufficient washing, the oxide film is airknife-dried up later to form a capacitor SiO2 and then a polysilicon electrode is formed to form an MOS capacitor.

公开(公告)号：JPS63202055A

公开(公告)日：1988-08-22

申请号：JP3387687

申请日：1987-02-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To make the difference in heights between wells nearly equal to zero and to make it possible to form a step required for patterning in succeeding steps, by forming both wells in a substrate by a self.aligning method, thereafter forming an epitaxial layer, and forming both wells in the epitaxial layer in the reverse order of the formation of both wells in the substrate. CONSTITUTION:A silicon nitride film in a P-type well region is removed and ions are implanted. Then, a P-type well region (i) is lower than an N-type well region (ii) by about a half a thermal oxide film. After an epitaxial layer 5 is formed, a thermal oxide film 6 and a silicon nitride film 7 are formed in the reverse order of the initial order. Patterning is performed so as to form an N-type well, and ions are implanted. Then, a thermal oxide film 9 is formed, and the silicon nitride film 7 is removed. Then ions are implanted in the P-type well, and the thermal oxide films 6 and 9 are removed. Then a step is not provided between both wells in the epitaxial layer 5. Thus a double-well structure, in which a step is formed only at the boundary part of the wells, is formed. In this way accurate patterning can be performed with a reducing-projection exposure apparatus. The threshold voltage values of P-type and N-type MOSFETs can be accurately controlled.

公开(公告)号：JPH03257830A

公开(公告)日：1991-11-18

申请号：JP5536990

申请日：1990-03-07

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI

IPC: H01L21/60 ,  H01L21/318

Abstract: PURPOSE:To avoid the damage of a silicon nitride film for improving a productive efficiency by doing away with the overlapping of an aluminum interconnection and the silicon nitride film at a wire-bonding section around an opening of the silicon nitride film. CONSTITUTION:A silicon oxide film 2 and an aluminum interconnection 3 which is formed on the surface of the silicon oxide film 2 on a silicon substrate 1 are covered with a silicon nitride film 4. Then, photo resist 5 is formed in the thickness of about 1.0mum and is heat-treated to protect the substrate 1 from light. After that, photo resist 6 is formed in the thickness of about 1.0mum to make an area wider than a wire-bonding metal interconnection section by the photolithography. Nextly, the photo resist and the silicon nitride film are removed by etching at the same etching ratio until the surface of the aluminum interconnection 3 at the wire-bonding section is exposed. Lastly, the remaining photo resist is removed by a normal method to obtain a desired semiconductor device.

公开(公告)号：JPS61263226A

公开(公告)日：1986-11-21

申请号：JP10518685

申请日：1985-05-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI

IPC: B08B3/02 ,  H01L21/304

Abstract: PURPOSE:To reduce an improper pattern by allowing liquid to continuously flow to the vicinity of the center of one main surface of a rotating wafer secured by a vacuum chuck, and simultaneously scanning the main surface with liquid of high speed to clean it, thereby removing the contaminants of particles. CONSTITUTION:Fluid 2 continuously flows to the vicinity of the center of one main surface of a rotating wafer 3 secured by a vacuum chuck 5. After a wafer film 4 is formed on the surface of the wafer 3, the liquid flow 1 of high speed is scanned on one main surface of the wafer 3. The fluid 2 is flowing water of flow rate of 100ml/min or more. Fluid 1 flows at initial speed of 100-150m/sec. Thus, contaminants of particles are removed to reduce an improper pattern.

公开(公告)号：JPH02294037A

公开(公告)日：1990-12-05

申请号：JP11427789

申请日：1989-05-09

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI

IPC: H01L21/60 ,  H01L21/321

Abstract: PURPOSE:To provide a reliable semiconductor device in which an aluminum wiring is not dissolved by making narrower an opening in an uppermost layer protective film than that in a lower layer protective film, and covering the end surface of the lower layer protective film. CONSTITUTION:A double-layer structure protective film comprises a silicon oxide film 3 and a silicon nitride film 4 both having a predetermined thickness, and an opening in the silicon nitride film 4 is made narrower and the end surface of the silicon oxide film 3 is completely covered. With such construction, water including impurities and ions, etc., is prevented by the silicon nitride film 4 and does not reach the silicon oxide film 3, so that dissolution of impurities such as phosphorus is eliminated and dissolution of an aluminum wiring 2 due to electrolysis of water including said impurities is also eliminated. Hereby, since dissolution of a wire bonding part of a metal wiring is eliminated, a market failure rate is reduced to assure a high reliability semiconductor device.

公开(公告)号：JPH08316241A

公开(公告)日：1996-11-29

申请号：JP12009295

申请日：1995-05-18

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI

IPC: H01L29/73 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/732

Abstract: PURPOSE: To obtain a self-aligned bipolar transistor whose electric characteristic is stabilized, whose productivity is enhanced and which can be operated at high speed without lowering a collector-to-base breakdown strength. CONSTITUTION: When the bottom face of a first base diffusion layer 9 is formed in a position which is deeper than the bottom face of a second base diffusion layer 16, the interval between the bottom face of the first base diffusion layer 9 and an n-type buried diffusion layer 2 can be made short without making the interval between the bottom face of the second base diffusion layer 16 and the n-type buried diffusion layer 2 short, and a transistor can be operated at high speed without lowering a collector-to-base breakdown strength. An oxide film 8 exists also on the formation region of an emitter diffusion layer 20 when a polycrystal silicon film 10 to be used as a base conductive film 18 is formed, the polycrystal silicon film 10 is formed on it, and an epitaxial layer 3 in the formation region of the emitter diffusion layer is protected by the oxide film 8 when the polycrystal silicon film 10 is dry-etched selectively.

公开(公告)号：JPH04107860A

公开(公告)日：1992-04-09

申请号：JP22578290

申请日：1990-08-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI

IPC: H01L27/00 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To make a semiconductor integrated circuit small by a method wherein a polysilicon film formed with a drain/source of a p channel MOS field-effect transistor directly comes into contact with a drain region of an n-channel planer MOS field-effect transistor. CONSTITUTION:A silicon oxide film 2 for separating an element, a gate insulating film 3 and a gate electrode 4 are formed on a p-type silicon substrate 1, an n-type self-aligning diffusion disposal is performed and an n-type diffusion region 5 is formed, whereby an n-channel planer MOS field-effect transistor 1A is formed. Next, an insulating film 6 between layers is formed, a polysilicon film 7 which is a gate electrode of a p-channel thin film MOS field-effect transistor 6A is formed, and a disposition is performed to make the n-type. Thereafter, a gate insulating film 8 of the p-channel thin MOS field-effect transistor 6A is formed and an opening 8A for coming into electric contact with a drain part of the silicon substrate is formed. Thereafter, a source, a drain, a channel part, and a silicon film 9 as a conductive layer in the p-channel thin film MOS field effect transistor 6A are formed.

公开(公告)号：JPH0389553A

公开(公告)日：1991-04-15

申请号：JP22633289

申请日：1989-08-31

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI ,  NISHIDA SOICHI

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/41 ,  H01L29/43

Abstract: PURPOSE:To eliminate necessity of disposing a contact hole apart from an element isolating region and to reduce the surface area of a semiconductor integrated circuit device by a structured in which a conductive film is formed between a metal wiring and a first n-type diffused region, a second n-type diffused layer is formed under the film, and the wiring is connected to the diffused layer through the film. CONSTITUTION:The surface of a p-type silicon substrate 1 is selectively oxidized to form an element isolating oxide film 2, a gate oxide film 3, and a gate electrode 4, an n -type diffused layer 5 is formed, and an interlayer insulating film 6 is further formed to complete an n-channel MOS transistor structure. Then, after a contact hole is formed in the film 6, a conductive film 7 is formed. The hole is so determined in size that the part is affected to the film 2, and part of the film 2 is removed at the time of formation of the hole. Phosphorus ions are implanted through the film 7, and an n -type diffused layer 8 is formed by heat treating. The layers 5, 8 are partly superposed to form a single n -type diffused layer. An interlayer insulating film 9 is formed, a contact hole is further formed, and metal wirings 10 are eventually formed.

公开(公告)号：JPH01128568A

公开(公告)日：1989-05-22

申请号：JP28790187

申请日：1987-11-13

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA KOJI ,  NISHIDA SOICHI

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/41

Abstract: PURPOSE:To increase a connecting area between metal wirings and a diffused layer and to increase the aligning margin of patterning a contact hole and the layer by connecting the wirings to the layer through a conductive film. CONSTITUTION:After an N-channel MOS transistor structure is completed, a contact hole is formed in an interlayer insulating film 6, and a conductive film, such as a polysilicon film 7 is formed. Then, phosphorus ions (P ) are implanted through the film 7, and further heat treated to activate it thereby to form an N type diffused layer 8. An N type diffused region is formed to the P-type silicon substrate of a section (a) as shown, and the film 7 is in ohmic contact with both N type diffused layers 5 and 8. Then, an interlayer insulating film 9 is formed, a contact hole for connecting the film 8 to the metal wirings is formed in the insulating film, and metal wirings, such as aluminum wirings 10 are eventually formed.