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    MANUFACTURE OF SEMICONDUCTOR DEVICE AND LEAD FRAME THEREFOR
    2.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR DEVICE AND LEAD FRAME THEREFOR 失效

    公开(公告)号：JPH10242182A

    公开(公告)日：1998-09-11

    申请号：JP3917097

    申请日：1997-02-24

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： NARAOKA HIROKI ,  TAGUCHI TOSHIAKI ,  NAKATSUKA KENJI

    IPC: H01L23/28 ,  H01L21/56 ,  H01L23/50

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and lead frame therefor which avoids mold resin-unfilled parts and improve the mass productivity of the semiconductor device. SOLUTION: A semiconductor chip 3 is adhered to a lead frame, which is then held between mold dies 4, mold resin 2 is injected from a mold gate 8 to fill the dies 4 with venting air through vent holes 5, and the dies are opened to take out a resin sealed and molded lead frame 1. Lead frame openings 7 are provided within the reach of the resin 2 injected in the air vents 5 of the lead frame 1 and upper and lower resin burrs 6 of the frame 1 are flowed into the openings 7 and mutually adhered.

    ANALYZING METHOD FOR SEMICONDUCTOR DEVICE
    3.
    发明专利
    ANALYZING METHOD FOR SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH03242951A

    公开(公告)日：1991-10-29

    申请号：JP4142790

    申请日：1990-02-21

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： NARAOKA HIROKI

    IPC: H01L21/306 ,  H01L21/66

    Abstract: PURPOSE:To enable measurement of the length of an impurity diffusion region by using mixed acid made by mixing hydrofluoric acid, nitric acid and acetic acid as etchant and by removing the impurity diffusion region of a low concentration selectively. CONSTITUTION:A cross section of a semiconductor device before etching which is divided by a surface parallel to a gate length direction of MOS transistors 1, 2 and parallel to the depth direction of a P-type silicon substrate 3 is etched by mixed acid made by mixing hydrofluorid acid, nitric acid and acetic acid at volumetric rate of 1:3:12; then, an arsenic diffusion region 7, phosphorus diffusion region 8 and a polysilicon film 4 which is doped with N-type impurities are etched. After etching, efective gate length X of the MOS transistor 1 can be measured visually through observation by scanning electron microscope, etc. Furthermore, since the phospherous diffusion region 8 is etched, a gate effective length Y of an MOS transistor 2 can be also measured visually through observation by a scanning electron microscope, etc. Thereby, the length of an impurity diffusion region can be measured.

    MANUFACTURE OF SEMICONDUCTOR DEVICE
    4.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS6430256A

    公开(公告)日：1989-02-01

    申请号：JP18557487

    申请日：1987-07-27

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： NARAOKA HIROKI ,  ITO RYOICHI

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/10

    Abstract: PURPOSE:Not only to prevent decrease in the element isolation breakdown strength or an adverse effect on the properties of a transistor due to the LOCOS or an etching performed onto a silicon substrate but also lessen the number of processes by a method wherein the ion-implantation is made to de through with one implantation of one kind of ions. CONSTITUTION:A silicon dioxide film 22 is formed on a primary face of a P-type silicon substrate 21 through the thermal oxidation and then a polycrystalline silicon film 23 is grown thereon, and phosphorus of an N-type impurity is doped thereto for the formation of an N-type MOS type electrode material 31. Next, a silicon dioxide film 32 is made to grow through a reduced- pressure chemical vapour deposition(LP-CVD) method, a photoresist 25 is patterned through a photolithography technique only on a region W where an N channel MOS type transistor of an LLD structure is to be formed, the anisotropic dry etching is performed onto an LP-CVD silicon dioxide film 32, the isotropic dry etching is performed onto a polycrystalline film 31 and then the ion-implantation of aresenic is performed, the LP-CVD silicon dioxide film 32 is removed, and thus a MOS type transistor is formed.

    PROCESSING OF SEMICONDUCTOR DEVICE
    5.
    发明专利
    PROCESSING OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS62118528A

    公开(公告)日：1987-05-29

    申请号：JP25897485

    申请日：1985-11-19

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： FURUTA KOJI ,  NARAOKA HIROKI

    IPC: H01L21/304 ,  H01L21/316

    Abstract: PURPOSE:To enable even drying up process to be performed while cutting water film evenly from the end of a wafer by a method wherein, in the cleaning process before sir-knife drying process, an oxide film is formed by chemical processing on an exposed substrate surface to be etched while leaving the oxide film. CONSTITUTION:When an MOS capacitor is formed, a LOCOS (SiO2) separating the capacitor and a pattern on an exposed Si substrate surface to be a capacitor coexist together on one main surface of a wafer. This wafer is cleaned up for the minutes in a cleaning solution with mixing ratio of e.g. NH4OH:H2O2:H2 O=1:2:7. An oxide film around 1mum thick is formed on Si by this cleaning process. After sufficient washing, the oxide film is immersed in a solution with mixing ratio of e.g. H2O:HF=500:1 to be etched by around 0.5mum leaving it by around 0.5nm. After sufficient washing, the oxide film is airknife-dried up later to form a capacitor SiO2 and then a polysilicon electrode is formed to form an MOS capacitor.

    SEMICONDUCTOR INTEGRATED DEVICE
    6.
    发明专利
    SEMICONDUCTOR INTEGRATED DEVICE 失效

    公开(公告)号：JP2000156462A

    公开(公告)日：2000-06-06

    申请号：JP32983998

    申请日：1998-11-19

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： HONMA FUTOSHI ,  TAKADA TAKASHI ,  NARAOKA HIROKI

    IPC: H01L25/18 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07

    Abstract: PROBLEM TO BE SOLVED: To obtain a thinner semiconductor integrated device which is high in productivity, low in cost, high in degree of freedom of chip design, capable of coping with a high-speed operation, and smaller in thickness than usual. SOLUTION: This semiconductor integrated device is equipped with a first semiconductor chip 10 whose element forming surface is fixed on the underside of a lead frame through a lead-on-chip, a second semiconductor chip 11 whose non-element forming surface is fixed to the top surface of a die pad 12 through an adhesive layer 16 without making its element forming surface or non-element forming surface confront that the first semiconductor chip 10, metal wires 17 and 18 which electrically connect the first semiconductor chip 10 and inter leads 13, and the second semiconductor chip 11 and inner leads 13 together respectively, and a sealing resin 19 which seals up the lead frame, semiconductor chips 10 and 11, and the metal wires 17 and 18.

    ELECTRONIC PART AND MANUFACTURE THEREFOR
    7.
    发明专利
    ELECTRONIC PART AND MANUFACTURE THEREFOR 失效

    公开(公告)号：JPH11251503A

    公开(公告)日：1999-09-17

    申请号：JP5165198

    申请日：1998-03-04

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： SAKAGUCHI SHIGEKI ,  IMAZU KENICHI ,  NARAOKA HIROKI ,  SAWADA TOMIZO ,  AOI KAZUHIRO

    IPC: H05K1/18 ,  H01L23/50

    Abstract: PROBLEM TO BE SOLVED: To solder parts easily firmly, by depositing a metal layer made of Sn containing Bi less than predetermined in percent on an electrode lead wire to be connected to the outside. SOLUTION: A metal layer made of Sn containing by weight less than 4% Bi is deposited on an electrode lead wire 5 connected to the outside as an outermost metal layer 6. A semiconductor element is die-bonded on a Cu lead frame and is provided with a wiring connected to an external electrode. An underlayer Ni-plated film is formed on the electrode lead wire 5 to be connected to the outside of the semiconductor device subjected to plastic sealing and lead forming, and then Bi is deposited on the metal underlayer as an Sn-Bi alloy film. This can make it possible to easily mount electronic parts on a printed substrate or a circuit substrate with solder at a low temperature and to improve the reliability of the portion bonded with solder.

    MANUFACTURE OF SEMICONDUCTOR DEVICE
    8.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH02181918A

    公开(公告)日：1990-07-16

    申请号：JP122089

    申请日：1989-01-09

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： HIRANO KANJI ,  NARAOKA HIROKI

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L23/52 ,  H01L29/78

    Abstract: PURPOSE:To prevent an oxide film from being left between a polycrystalline silicon layer and a tungsten silicide layer and to prevent an impurity layer from being formed by a method wherein polycrystalline silicon and tungsten silicide which is used as a wiring part are grown continuously inside an identical growth furnace. CONSTITUTION:A LOCOS isolation region 1 and a transistor formation region 2 are formed on a P-type semiconductor substrate. This assembly is oxidized in an oxygen atmosphere; a gate oxide film 3 is formed. A polycrystalline silicon layer 4 doped with phosphorus is formed by using SiH4 gas and PH3 gas. Then, the inside of a reaction furnace is once set to a high vacuum state; residual gases and impurities are removed sufficiently; after that, a layer 5 is formed by using SiH2Cl2 gas and WF6 gas. After the silicon layer 4 has been grown, it is not taken out from a growth chamber; the layer 5 is grown in succession; accordingly, an oxide film and an impurity layer are not formed between both layers; an interface between both layers is stabilized chemically and physically; it is possible to maintain the film 5 in a stable state against a high-temperature heat treatment in a posterior process.

    SUCTION MOVING DEVICE FOR SEMICONDUCTOR SUBSTRATE
    9.
    发明专利
    SUCTION MOVING DEVICE FOR SEMICONDUCTOR SUBSTRATE 失效

    公开(公告)号：JPH0290647A

    公开(公告)日：1990-03-30

    申请号：JP24350788

    申请日：1988-09-28

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： NARAOKA HIROKI

    IPC: H01L21/677 ,  H01L21/68

    Abstract: PURPOSE:To eliminate a problem in the suction of water content from a vacuum tweezers and moreover, to make possible the carrying-in of a water jet pump to a semiconductor device manufacturing field as well to make short the distance of a piping and to make possible a reduction in the cost of a motive power as well by a method wherein a negative pressure generation source is replaced with the water jet pump. CONSTITUTION:When the surface of a semiconductor substrate is sucked by a suction part of a vacuum tweezers 2 in the water, water content is sucked in completely from the suction part, but the sucked water component joins the water content of a motive power and is excluded by a water jet pump 1 and the suction from the suction part does hardly cause a problem in a reduction in the power of the pump itself. Moreover, as a rotation part is unnecessary for the pump 1 and oil content for preventing an overheating due to the friction of a rotating axis is also never used, the pump results in being carried in to a semiconductor device manufacturing field as well without worries about contamination and a piping 3 also can be sufficed at a short distance. Furthermore, as both a rise and a fall of the operation of the pump 2 can be executed instantaneously and stably by opening and shutting a valve 5, a wasteful motive power can be omitted by interrupting rapidly a water current source 4 by the valve 5 when the pump is unnecessary.

    MANUFACTURE OF MOS INTEGRATED CIRCUIT
    10.
    发明专利
    MANUFACTURE OF MOS INTEGRATED CIRCUIT 失效

    公开(公告)号：JPS63219152A

    公开(公告)日：1988-09-12

    申请号：JP5255687

    申请日：1987-03-06

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： NARAOKA HIROKI

    IPC: H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    Abstract: PURPOSE:To reduce the formation processes of photoresist films by a method wherein an element formation region is covered with a photoresist films to successively form a diffused region in high impurity concentration and another diffused region in low impurity concentration. CONSTITUTION:The parts excluding p well region forming N channel MOSFET in LDD structure are covered with a photoresist film 7; N type diffused regions 15 in high impurity concentration to be a source region and a drain region of N channel are formed into P well region 2; successively spacers 13 on both end sidewalls of gate electrode 6 are removed to form N type diffused region 8 in low impurity concentration to be a source region and a drain region of N channel. Finally, the photoresist film 7 is removed; the parts excluding the N well region 3 are covered with another photoresist film 14; and a p type diffused layer 17 in high impurity concentration and another p type diffused layer 10 in low impurity concentration are formed in the N well region 3.

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