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    Method of manufacturing high breakdown voltage rectifiers
    1.
    发明授权
    Method of manufacturing high breakdown voltage rectifiers 失效
    制造高耐压整流器的方法

    公开(公告)号：US3929531A

    公开(公告)日：1975-12-30

    申请号：US36008073

    申请日：1973-05-14

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： HATTORI HIROTSUGU ,  TAKAYAMA YUICHIRO

    IPC: H01L21/306 ,  H01L25/07 ,  H01L29/00 ,  H01L21/304

    CPC classification number: H01L25/074 ,  H01L21/30604 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/054 ,  H01L2924/00

    Abstract: A method of manufacturing rectifying device by cutting a lamination of semiconductor wafers each having a P-N junction formed therein along planes perpendicular to the plane of the wafer and subjecting the resultant divided series diode laminations to an etching treatment with a blend etching liquid composed of hydrogen fluoride, nitric acid and acetic acid. The etching liquid strongly acts upon the N-type region, while it weakly acts upon the P-type region, so that a configuration similar to that which would be obtained through a positive bevel treatment may be obtained. Thus, it is possible to obtain a high breakdown voltage rectifier which is hardly subject to destruction due to a transient reverse voltage.

    Abstract translation: 一种通过切割每个具有PN结的半导体晶片的层压制造整流装置的方法，所述半导体晶片具有垂直于晶片平面的平面，并且使所得到的分割的二极管叠层用由氟化氢组成的混合蚀刻液进行蚀刻处理 ，硝酸和乙酸。 蚀刻液体强烈地作用在N型区域上，而弱作用在P型区域上，因此可以获得与通过正斜面处理获得的结构相似的构造。 因此，可以获得由于瞬态反向电压几乎不被破坏的高击穿电压整流器。

    CONTACT STRUCTURE FOR SECURING A SEMICONDUCTOR SUBSTRATE TO A MOUNTING BODY
    4.
    发明专利
    CONTACT STRUCTURE FOR SECURING A SEMICONDUCTOR SUBSTRATE TO A MOUNTING BODY 未知

    公开(公告)号：CA1189984A

    公开(公告)日：1985-07-02

    申请号：CA406337

    申请日：1982-06-30

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： HATTORI HIROTSUGU ,  KUWAGATA MASAHIRO

    IPC: H01L21/52 ,  H01L21/58 ,  H01L21/60 ,  H01L23/492 ,  H01L23/14

    Abstract: A contact structure for securing a semiconductor substrate to a mounting body in a semiconductor device. A multi-layered electrode formed on a surface of the semiconductor substrate, the multi-layered electrode comprising a chromium-nickel alloy layer formed on the surface, a nickel layer formed thereon and a noble metal layer selected from the group consisting of gold, silver, palladium and platinum formed further thereon, a solder layer, and a mounting means for holding the semiconductor substrate thereon, the solder layer soldering the multi-layered electrode to the mounting means, thereby bonding the semiconductor substrate to the mounting means. The foregoing construction has the features that there are substantially no voids at the solder layer as a result of good wetting of the noble metal to the solder layer; that the effective bonding area increases as a result of decrease of voids, resulting in decrease of thermal resistance by 10 to 20%; that secondary breakdown voltage increases by about 10%, thereby increasing reliability; that the bonding force is drastically increased; that process control in the soldering step becomes easier; that undesirable Sn-Ni formation is suppressed, thereby improving resistivity to thermal fatigue; and that oxidation of the surface of the multi-layered electrode is eliminated, thereby eliminating the necessity for preliminary treatment before soldering.

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