公开(公告)号：JPH0274073A

公开(公告)日：1990-03-14

申请号：JP22673988

申请日：1988-09-09

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO RYOICHI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/336 ,  H01L23/52 ,  H01L29/43 ,  H01L29/78

Abstract: PURPOSE:To prevent a high melting point metal silicide film from separating off and to enable signals to propagate at a high speed by a method wherein a second silicon nitride film is formed along both the side walls of the high melting point metal silicide film and a first silicon nitride film. CONSTITUTION:A high melting point metal silicide film 14 possessed of stoichiometrically excessive silicon atom is formed on a semiconductor substrate 11, a first silicon nitride film 15 used as a mask to process the film 14 into a specified form is formed, and the high melting point metal silicide film 14 and the first silicon nitride film 15 are subjected to a patterning process. And, a second silicon nitride film 16 is formed along both the side walls of the high melting point metal silicide film 14 and the first silicon nitride film 15 after the patterning of them. By this setup, the high melting point metal silicide film can be prevented from separating off through a heat treatment process executed for the activation and the oxidation of the region of an impurity diffusion layer, so that signals can be propagated at a high speed.

公开(公告)号：JPS6430256A

公开(公告)日：1989-02-01

申请号：JP18557487

申请日：1987-07-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NARAOKA HIROKI ,  ITO RYOICHI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/10

Abstract: PURPOSE:Not only to prevent decrease in the element isolation breakdown strength or an adverse effect on the properties of a transistor due to the LOCOS or an etching performed onto a silicon substrate but also lessen the number of processes by a method wherein the ion-implantation is made to de through with one implantation of one kind of ions. CONSTITUTION:A silicon dioxide film 22 is formed on a primary face of a P-type silicon substrate 21 through the thermal oxidation and then a polycrystalline silicon film 23 is grown thereon, and phosphorus of an N-type impurity is doped thereto for the formation of an N-type MOS type electrode material 31. Next, a silicon dioxide film 32 is made to grow through a reduced- pressure chemical vapour deposition(LP-CVD) method, a photoresist 25 is patterned through a photolithography technique only on a region W where an N channel MOS type transistor of an LLD structure is to be formed, the anisotropic dry etching is performed onto an LP-CVD silicon dioxide film 32, the isotropic dry etching is performed onto a polycrystalline film 31 and then the ion-implantation of aresenic is performed, the LP-CVD silicon dioxide film 32 is removed, and thus a MOS type transistor is formed.

公开(公告)号：JPH02117175A

公开(公告)日：1990-05-01

申请号：JP26946188

申请日：1988-10-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SATO KAZUO ,  YOKOZAWA KENJI ,  UCHIDA SHINICHI ,  ITO RYOICHI ,  KOJIMA MAKOTO

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To increase the withstand voltage of an MIOS semiconductor memory by providing the first region touching the end section of a channel region directly, and the second region touching the first region and having impurity density higher than that of the first region. CONSTITUTION:N diffusion regions 7, 8 and N diffusion regions 9, 10 are formed in a P-type silicon substrate 1; thin silicon oxide film 4 is provided spreading over the N diffusion regions 9, 10; a silicon nitride film 5 and a gate electrode 6 are laminated on the thin silicon oxide film 4 in this order; and besides lateral wall films 11 made from silicon oxide films are provided at the sides of the gate section. This constitution lightens the electric field concentration in the channel regions in the vicinities of the drain and source regions of MIOS semiconductor memories, and makes it possible to enhance the voltage-withstanding characteristics.

公开(公告)号：JPH02103966A

公开(公告)日：1990-04-17

申请号：JP25758388

申请日：1988-10-13

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO RYOICHI ,  UCHIDA SHINICHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To form a semiconductor memory device having high memory holding characteristics by forming a silicon nitride film, a second silicon dioxide film and a gate electrode on a first silicon dioxide thin film which is to become a tunneling medium, and performing fluorine-ion implantation and heat treatment. CONSTITUTION:On a semiconductor substrate 1, a thin first silicon dioxide film 2 which is to become a tunneling medium, a silicon nitride film 6 which is to become an insulating film, a second silicon dioxide film 7 and a gate electrode 8 are laminated and formed. With the electrode 8 as a mask, a source region 9 and a drain region 10 are formed by the implantation of N-type impurities. Heat treatment is performed in N2 gas, and the regions 9 and 10 are activated. Thereafter, fluorine ions F which are stabler than hydrogen are implanted. Heat treatment is performed in N2 gas, and the ions are activated. A semiconductor memory device having high memory holding characteristics is formed by the method for implanting the stable fluorine ions.

公开(公告)号：JPH02307277A

公开(公告)日：1990-12-20

申请号：JP12976389

申请日：1989-05-22

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO RYOICHI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To make the uniformity of a natural oxide film favorable, and to improve the uniformity of a thin oxide film so that it may prevent the variation of initial threshold voltages on the elimination side being the electric characteristics of the MNOS transistor of an EAROM by introducing a process of cleaning the surface of an exposed substrate in cleaning solution based on hydrogen peroxide. CONSTITUTION:The process of exposing the surface of a substrate 11 by chemically etching and removing a first oxide film 13 provided at the surface of a semiconductor substrate 11 of one conductivity type, the process of cleaning the surface of the exposed substrate 11 in cleaning solution based on hydrogen peroxide, and the process of providing a second oxide film 15 at the surface of the cleaned substrate 11 are provided. For example, the surface of the Si substrate 11 is exposed by etching the oxide film 13 with buffered hydrofluoric acid, and the surface of the Si substrate 11 is cleaned at a temperature of 60-80 deg.C for 15 minutes in the cleaning solution of H2O2:NH4OH:H2 O=1:1:8. Next, the second thin oxide film 15 is oxidized at 600-700 deg.C for 2 hours in oxygen gas atmosphere and is made into the thickness of 5nm or below, and thereon a nitride film 16 about 20nm thick and the second polycrystalline silicon 17 doped with phosphorus are formed.

公开(公告)号：JPH02103965A

公开(公告)日：1990-04-17

申请号：JP25758288

申请日：1988-10-13

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO RYOICHI ,  UCHIDA SHINICHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To improve memory holding characteristics by forming a silicon nitride film by a vapor phase method utilizing plasma excitation reaction after the formation of a gate electrode, and thereafter performing fluorine ion implantation, heat treatment and the like. CONSTITUTION:A gate electrode layer 8 is formed on a first silicon nitride film comprising a silicon nitride film 6 and a silicon dioxide film 7 on a P-type silicon semiconductor substrate 1. Then, second silicon nitride film comprising a silicon dioxide film 11 and a silicon nitride film 12 is formed at 800 deg.C less than 900 deg.C where the quality of the silicon nitride film is changed by a vapor growth method based on plasma excitation reaction. Thereafter, fluorine ions F are implanted, and heat treatment is performed. When the ions are activated, unbonded Si atoms in the first silicon nitride film are decreased. Decomposition of the silicon nitride film does not occur. The memory holding characteristics are enhanced through the silicon nitride film by the decrease in unbonded Si atoms in the silicon nitride film.

公开(公告)号：JPS61263243A

公开(公告)日：1986-11-21

申请号：JP10519185

申请日：1985-05-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUKUCHI JUN ,  YOKOZAWA KENJI ,  ITO RYOICHI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/283 ,  H01L23/52

Abstract: PURPOSE:To form a gate electrode having good sealability by depositing a WSix film which contains excess Si, a WSix film which contains less Si, and a WSix film which contains excess Si on a primary oxide film, and further annealing them. CONSTITUTION:The main surface of an Si substrate 1 is selectively oxidized to form a LOCOS oxide film 2. Then, a gate oxide film 3 is formed in a high temperature oxidative atmosphere. Thereafter, a WSi3.1 film 4 is deposited, a WSi2.6 film 5 is then deposited, and a WSi3.1 film 4 is further deposited. They are then annealed, patterned to dry-etch the WSix films, thereby forming electrodes.

公开(公告)号：JPH03242940A

公开(公告)日：1991-10-29

申请号：JP4000190

申请日：1990-02-21

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO RYOICHI

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

Abstract: PURPOSE:To improve the stability of the width of a gate electrode and the reliability of an element by forming the gate electrode on a semiconductor substrate whereon a gate oxide film is formed, by forming a source region and a drain region by ion implantation and by forming a silicon nitride film on the both side walls of the gate electrode afterward by a reduced pressure CVD method or the like. CONSTITUTION:After an oxide film 2 is formed by oxidizing selectively one main surface of a silicon substrate 1 of a P type (100), a gate oxide film 3 is formed in an oxidizing atmosphere of high temperature, boron ions are implanted and then a polycrystalline silicon film 4a is made to grow. Moreover, a gate electrode 4 is formed by subjecting the polycrystalline silicon film 4a to dry etching, first ion implantation is executed to form a first source region 5 and a first drain region 6, and then a reduced pressure CVD method and anisotropic dry etching are applied, so as to form silicon nitride films 7 and 8 along the both side walls of the gate electrode 4. Next, heat treatment is conducted in the atmosphere of water vapor, an oxide film 9 is made to grow and a second source region 10 and a second drain region 11 are formed. By this method, the stability of the width of the gate electrode and the reliability of an element can be improved.

公开(公告)号：JPH0320086A

公开(公告)日：1991-01-29

申请号：JP15539489

申请日：1989-06-16

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ITO RYOICHI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To prevent a tungsten silicide film of high melting point from peeling by patterning a conductive layer which becomes a floating gate electrode to a specified shape and thereafter by flattening a stepped section whose edge section overrides a thick oxide film. CONSTITUTION:A LOCOS oxide film 12 and a gate oxide film 13 are formed on an Si substrate 11, and then a first layer of a polycrystalline silicon film 14 is made to grow through CVD method. A BPSG film 15 is formed as an insulating film and patterned. A section excepting a stepped section is removed through wet etching, and heat treatment is carried out in a high temperature oxide atmosphere of oxygen and hydrogen gas. A gate oxide film 16 is formed on a first layer of a polycrystalline silicon film 14 and a substrate 11 while the BPSG film 15 is thermally melted to flatten the stepped section. Then, a second layer of a polycrystalline silicon film 17 and a tungsten silicide film 18 of high melting point are formed. It is possible to prevent the tungsten silicide film 18 from peeling in this way.

公开(公告)号：JPH02292835A

公开(公告)日：1990-12-04

申请号：JP11343289

申请日：1989-05-02

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UCHIDA SHINICHI ,  ITO RYOICHI

IPC: H01L21/50 ,  H01L21/56

Abstract: PURPOSE:To make it possible to prevent the intrusion of an impurity into the interior of a device and to make it possible to contrive the improvement of the reliability of the device by a method wherein after coupling members for supporting member use exposed from a first insulator are cut and removed, the surface of the first insulator and the cut surfaces of the coupling members are covered with a second insulator and the like. CONSTITUTION:A semiconductor device main body 1 is placed on a supporting member 3 of a lead frame 2 provided by coupling the member 3 for supporting the main body 1, a plurality of coupling members 4 for supporting member use and a plurality of lead members 5 for electrode use with one another and the main body 1 and the inner end parts of the members 5 are connected to each other by metallic wirings 6. Then, after the main body 1, the member 3, the wirings 6 and the inner end parts of the members 5 are integrally covered with a first insulator 7, the members 4 exposed from the insulator 7 are cut and removed. Then, after the outer end parts of the members 5 are exposed and the surface of the insulator 7 and cut surfaces 4a of the members 4 are covered with a second insulator 8, the members 5 are left and the lead frame 2 is removed.