公开(公告)号：JPH03133154A

公开(公告)日：1991-06-06

申请号：JP27042089

申请日：1989-10-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L21/76 ,  H01L21/316

Abstract: PURPOSE:To restrain transverse enlargement of an insulating film of an isolation region by forming an insulating film for isolation by applying etching and a low pressure chemical thin film formation method. CONSTITUTION:After an upper part of a semiconductor substrate 1 is covered with a nitride film 3, an isolation region is etched to form a vertical step 4; impurity ions are implanted; an insulating film 5 is made to form all over by a low pressure chemical thin film formation method; and the nitride film 3 and the step 4 are buried. After surfaces of the nitride film 3 on an isolation region and insulating films 5, 6 on the isolation region are flattened by etching, heat treatment is applied to build up an oxide film 7 on an insulating film alone and to form an isolation isolating film 8. Thereby, it is possible to form an isolation film 8 inside the isolation region accurately and to restrain transverse enlargement of the insulating film 8.

公开(公告)号：JPH06125044A

公开(公告)日：1994-05-06

申请号：JP27566792

申请日：1992-10-14

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L27/06 ,  H01L21/8249

Abstract: PURPOSE:To make the number of manufacturing process steps and the number of photomasks required for a BICMOS device nearly equal to those required for the CMOS device while the significance of the BICMOS device is secured. CONSTITUTION:By forming an N-type buried layer 17 and P-type buried layer 18 by performing simultaneous diffusion by using one photomask and increasing the surface concentration of a P-type well layer 21 twice or thrice, the parasitic characteristics immediately below a LOCOS film 22 are maintained at nearly the same level as the conventional example and, at the same time, the LOCOS film 22 is incorporated in a bipolar element by controlling the threshold of a MOS transistor without using any special photomask for controlling the threshold. As a result, no characteristic variation results in. Therefore, a BICMOS device can be formed by increasing the number of photomasks by one from that required for forming the CMOS device and the number of manufacturing process steps can be remarkably reduced as compared with that required by the conventional BICMOS device manufacturing method.

公开(公告)号：JPH06349942A

公开(公告)日：1994-12-22

申请号：JP13750893

申请日：1993-06-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L21/76 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06

Abstract: PURPOSE:To prevent a parasitic MOS transistor from decreasing in threshold voltage and increasing in leakage current by a method wherein buried layers are made different from each other in impurity concentration, and a channel stopper is formed taking advantage of the level difference between the upper ends of the buried layers. CONSTITUTION:A first P -type buried layer 23 and a second P -type buried layer 24 are formed on a P-type semiconductor substrate 21 through a double resist method. An N -type well diffusion layer 25, an N--type well diffusion layer 26, and a P -type well diffusion layer 27 are formed, furthermore the second P -type buried layer 24 is made higher than the first P -type buried layer 23 through a thermal treatment performed in a LOCOS film 28 growing process so as to reach under the LOCOS film 28, and the second P -type buried layer 24 is made to serve as the channel stopper of an effective N-channel parasitic MOS transistor, By this setup, a parasitic MOS transistor can be prevented from decreasing in threshold voltage and increasing in leakage current, and thus a Bi-CMOS device of low cost can be realized.

公开(公告)号：JPH0575026A

公开(公告)日：1993-03-26

申请号：JP23211791

申请日：1991-09-12

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L27/04 ,  H01L21/822

Abstract: PURPOSE:To completely flatten a resistor element by suppressing variation in resistance value by the heat treatment in after process, and simplifying the control of the resistance value of a polysilicon film of high resistance. CONSTITUTION:A groove having a certain curvature is made in a semiconductor substrate 1, and a thermal oxide film 4 and a nitride film 5 are formed in order, and then, a polysilicon film 6 is charged in the groove, and the polysilicon film 6 on the surface excluding the groove is removed by etchback, and further a nitride film 8 is formed on the polysilicon film 6, and a CVD film 9 is formed on this nitride film 8, and a contact window is formed on the polysilicon film 6, and aluminum wiring 10 is formed on this contact window.

公开(公告)号：JPS6442152A

公开(公告)日：1989-02-14

申请号：JP19853487

申请日：1987-08-07

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L21/31 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE:To make through hole resistance the same as multilayer interconnection process using an inorganic material, by using a photosensitive polyimide resin as an interlayer insulating film of a multilayer interconnection and providing O2 plasma treatment before the interconnections of layers are connected. CONSTITUTION:Any device structure is formed on a silicon semiconductor substrate 1, and then a first interconnection 3 of aluminum is formed through a silicon dioxide film 2 thereon. Then, a photosensitive polymide resin 4 is applied and prebaked. A through hole pattern is formed by photolithography technique and ashed with O2 plasma 5 on the whole surface. Then, an aluminum interconnection of the second layer is deposited and a second interconnection 6 is patterned by the photolithography technique. As a result, it is possible to completely eliminate a residual element of the photosensitive polymide resin and impurities on the through hole pattern.

公开(公告)号：JP2001144258A

公开(公告)日：2001-05-25

申请号：JP32555899

申请日：1999-11-16

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To realize mounting of a capacitance element which relaxes the concentration of electric field, after a nitride film which is used as an insulation film of capacitor is deposited, by controlling the polysilicon surface condition to reduce the degree of projection of polysilicon. SOLUTION: When doping an impurity to a polysilicon film formed on an oxide film for element isolation, a sheet resistance value of the polysilicon film is adjusted by adjusting the doping time to control roughness of the polysilicon film surface. The surface roughness can be set to 20 nm or less, and a lower sheet resistance may be assured to manufacture a highly reliable and highly accurate capacitance element, by setting the impurity doping time to 30 minutes or less.

公开(公告)号：JPH11297935A

公开(公告)日：1999-10-29

申请号：JP9616998

申请日：1998-04-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI ,  NABESHIMA TAMOTSU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To reduce dispersion in resistance value and to make adjustment of resistance value easy. SOLUTION: With a constant distance C assured in an element formation region 11a, a trimmed pattern is formed with the pattern of a CVD film 13 comprising the same conductivity as a gate electrode, and, a P-type impurities is doped with the trimmed pattern and a P+ type diffusion resistor formation pattern 15a as masks to form a P+ type diffusion resistor layer 15 for reduced dispersion in resistance value, and, selection of impurity dope process for forming resistance allows adjustment of diffusion resistor width, resulting in easy adjustment of resistance value.

公开(公告)号：JPH03211872A

公开(公告)日：1991-09-17

申请号：JP745890

申请日：1990-01-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06

Abstract: PURPOSE:To improve high frequency characteristic of a bipolar transistor, to improve breakdown strength of a MOS transistor and to form an accurate capacitance element by employing a nitrite film. CONSTITUTION:In order to improve high frequency characteristic of bipolar transistor, a field film between an emitter 9 and a base 8 is formed of a nitrite film 11. Then, elements of a MOS transistors are isolated by an isolating method by a combination of an element isolating oxide film (LOCOS film) 14 and the film 11, and further a capacitance element structure is formed of an MNS capacitance using the film 11. Thus, the high frequency characteristic of the bipolar transistor is improved, an element isolating breakdown strength upon high integration of the MOS transistor is improved, and a capacitance element having an MNS(Metal-Nitrite-Semiconductor) structure is obtained as a capacitance element having a high accuracy and high unit capacitance.

公开(公告)号：JPH02280369A

公开(公告)日：1990-11-16

申请号：JP10284789

申请日：1989-04-20

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L27/04 ,  H01L21/822

Abstract: PURPOSE:To contrive the enhancement in capacity without increasing the area by forming a MOS capacity and a MIS capacity at one time on a pattern and connecting them in parallel. CONSTITUTION:A polycrystalline silicon film 7 is deposited on a thin thermal oxide film 6 on a semiconductor substrate 1 by a LPCVD technique and a desired pattern is formed by photolithography and etching, immediately after which a silicon nitride film 9 is grown on said film 7 uniformly by the LPCVD technique. Then, a desired pattern is formed by photolithography and etching and a metal 12 is deposited by spattering. Next, the pattern formation is effected by photolithography and etching and electrodes are led out from each of the substrate 1, the film 7, and the film 9 and a MOS capacity and a MIS capacity are formed at the same time which are then connected in parallel.

公开(公告)号：JPH02162729A

公开(公告)日：1990-06-22

申请号：JP31750488

申请日：1988-12-15

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213

Abstract: PURPOSE:To form an excellent wiring pattern using a mirror projection exposure device without using a high performance reduction projection aligner by a method wherein an aluminum wiring layer is patterned using a resist and a PSG film as masks. CONSTITUTION:Within a MOS type transistor comprising a P-type diffused layer 7, a gate oxide film 8, a polysilicon gate electrode 9 on an N type semiconductor substrate 6, an insulating film 10 containing no impurity such as silicon is formed on the surface of the substrate 6 and then a PSG film 11 is formed on the film 10. Next, an aluminum wiring layer 12 is deposited on the surface of the PSG film 11 and further the other PSG film 13 is deposited on the surface of the layer 12; the film 13 is coated with a resist 14; the PSG film 13 is etched away with RIE process using the resist 14 as a mask; and then a part of the surface of the aluminum wiring 12 is exposed. Later, the aluminum wiring layer 12 is etched away using the resist 14 and the PSG film 13 as masks. Finally, the resist 14 and the PSG film 13 are removed thereby the patterned aluminum wiring 12 is formed. In the said photomasking process, an excellent wiring shape can be made using even a mirror projection exposure device without using a high performance reduction projection aligner.