公开(公告)号：JPH11297810A

公开(公告)日：1999-10-29

申请号：JP9772298

申请日：1998-04-09

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NABESHIMA TAMOTSU ,  YAMAZAKI HIROKANE

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To facilitate an embedding of isolation grooves and a flattening of the isolation grooves without adding a complicated process to a method of manufacturing a semiconductor device, and to make it possible to form locally channel stopper layers. SOLUTION: A semiconductor device is constituted into such a structure that insulating films 5 are deposited on a semiconductor substrate 1 having a surface protective film, which consists of an SiO2 film 2 and a polysilicon film 3, and isolation grooves 4 so that the films 5 do not meet each other in the interiors of the grooves 4 and thereafter, the films 5 are subjected to anisotropic etching so that the sidewalls of the grooves 4 are not exposed and the bottoms only of the grooves 4 are made to expose. Then, an impurity- containing SOG material 6 is applied on the substrate 1, a heat treatment is applied to the material 6 to form an SOG film 108 on the material 6 and at the same time, impurities are diffused from the material 6 in the bottoms of the grooves 4 to form channel stopper layers 7 on the bottoms of the grooves 4 and thereafter, the film 8 is etched back and the surface protective film is removed in order.

公开(公告)号：JPH11297935A

公开(公告)日：1999-10-29

申请号：JP9616998

申请日：1998-04-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： JIN YASUSHI ,  NABESHIMA TAMOTSU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To reduce dispersion in resistance value and to make adjustment of resistance value easy. SOLUTION: With a constant distance C assured in an element formation region 11a, a trimmed pattern is formed with the pattern of a CVD film 13 comprising the same conductivity as a gate electrode, and, a P-type impurities is doped with the trimmed pattern and a P+ type diffusion resistor formation pattern 15a as masks to form a P+ type diffusion resistor layer 15 for reduced dispersion in resistance value, and, selection of impurity dope process for forming resistance allows adjustment of diffusion resistor width, resulting in easy adjustment of resistance value.

公开(公告)号：JP2000236092A

公开(公告)日：2000-08-29

申请号：JP3775799

申请日：1999-02-16

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NABESHIMA TAMOTSU ,  MATSUI YASUSHI

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To increase the breakdown voltage of a semiconductor device without increasing the number of processes, and to provide an HVMOS that can be mixedly mounted, a semiconductor device using it, and its manufacturing method. SOLUTION: On an n-epitaxial layer 1, p field relaxation layer and p-well layer 2 and 3, and n-well layers 4 and 5 are formed simultaneously. Then, a LOCOS oxide film 6 is formed, and p low-concentration diffusion layers 7 and 8 are formed simultaneously. A gate oxide film 9 and a gate polysilicon film 10 are formed successively, and a sidewall 11 is used for simultaneously forming an n-source/drain region 12 and an n-well region 13, and p-source/drain regions 14 and 15. Finally, a first interlayer insulating film 16 is formed, source/drain electrodes 17, 18, and 19 are formed simultaneously, and a second interlayer insulation 20 and a second drain electrode 21 are formed successively. The source electrode 18 is formed, while the source electrode covers the entire gate polysilicon film 10, and the second drain electrode 21 is formed so as to overlap with the end of the source electrode 18.

公开(公告)号：JP2000232224A

公开(公告)日：2000-08-22

申请号：JP3256099

申请日：1999-02-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NABESHIMA TAMOTSU ,  MATSUI YASUSHI

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To raise the breakdown voltage of a high-breakdown voltage field effect transistor (DMOSFET). SOLUTION: This semiconductor device is constituted into a structure, wherein a gate electrode 106C for DMOS is formed on an N-type epitaxial layer 101 on a semiconductor substrate 100. After a P-type body layer 107 is formed in such a way as to extend up to under the lower part of the electrode 106C in the side on one side of the sides of the electrode 106C on the layer 101, a source layer 109 for DMOS having an N-type first low-concentration impurity layer 109a, and an N-type first high-concentration impurity layer 109b which is encircled with the layer 109a, is formed in such a way that the layer 109 is encircled with the layer 107. A drain layer 110 for DMOS is formed in such a way that the layer 110 is separated from the electrode 106 on the other side of the electrode 106C on the layer 101. A source electrode 115 is formed in such a way that the end parts of the electrode 106C are covered with the electrode 115.

公开(公告)号：JPH0945668A

公开(公告)日：1997-02-14

申请号：JP19853295

申请日：1995-08-03

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NABESHIMA TAMOTSU

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To provide a chemical dry etching method in which a side-etched part is not generated at the bottom end part of a contact hole when a damaged layer on the bottom face of the contact hole is removed and in which a resist ashing means is not required separately. SOLUTION: An insulating film 2 which is formed on the surface of a semiconductor substrate 1 is dry-etched selectively while a resist 3 which is formed on it is used as a mask. A contact hole 4 is formed in the insulating film 2. After that, a chemical dry etching operation is performed by using a mixed gas which is mixed at a mixture ratio that the volume flow rate ratio of carbon fluoride gas to oxygen gas is 0.8 or higher and 2.0 or lower. Thereby, since a side-etched part is not formed at the bottom end part of the contact hole, the disconnection of a barrier metal is prevented. As a result, a junction leak caused by the generation of an alloy pit is eliminated.