公开(公告)号：JP2000138165A

公开(公告)日：2000-05-16

申请号：JP21459399

申请日：1999-07-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: H01J37/305 ,  G03F7/20 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To prevent fatal deformation in a circuit pattern without lowering throughput even if a connection error occurs between partial irradiation regions. SOLUTION: At first, until forming beams 21 reach from a region at a lower left corner of a circuit pattern 16a to an upper left region, a substrate stage 12 and a mask stage 17 are continuously moved to a -Y direction, while the forming beams 21 are irradiated, thereby obtaining a partial irradiation region 22. After the forming beams 21 reached an upper left region of the circuit pattern 16a, the substrate stage 12 and mask stage 17 are slid to a -X direction by a pitch P. Until the forming beams 21 reach from an upper end part of the circuit pattern 16a to a lower end thereof, the substrate stage 12 and mask stage 17 are continuously moved to a +Y direction. At this time, the forming beams 21 are formed so that an irradiation amount of a double irradiation part 22a of the partial irradiation region 22 is equaled with that of a non-double irradiation part 22b thereof.

公开(公告)号：JP2001007018A

公开(公告)日：2001-01-12

申请号：JP2000106116

申请日：2000-04-07

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU ,  WATANABE HISASHI

IPC: G03F7/20 ,  H01J37/305 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To obtain a resist pattern having a prescribed shape by preventing the deformation of the resist pattern, caused by connection errors between partial exposure regions when a charged particle beam is used. SOLUTION: First, design data corresponding to a designed pattern are divided into a first stripe region group 61 composed of three stripe regions 61a-61c in a data arrange region 10. Then, the design data in matching with one of the stripe regions 61a-61c are extracted from a plurality of design data as a first design data group, and the group is prepared as first lithography pattern data. Then design data which spread over a plurality of regions of the first stripe region group 61 are extracted as a second design data group. Thereafter, a second strip region 62 which matches design data 16 and is different from the first stripe region group 61 is provided in the data arrange region 10.

公开(公告)号：JP2000181045A

公开(公告)日：2000-06-30

申请号：JP35109498

申请日：1998-12-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: H01L21/027 ,  G03F1/36 ,  G03F1/68 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To correct light proximity effect with high accuracy. SOLUTION: In a test pattern measuring process (ST12), the size of a test pattern transferred onto a wafer is measured. In a process variation calculating process (ST13), ±5% variation in, for example, exposure quantity and ±0.45 μm defocusing from among the variation quantities of various parameters in an actual process are supposed, and it is assumed that variation factors like those have regular distributions. In a size distribution and mean value acquiring process (ST14), size distribution characteristics are obtained and then mean values are calculated by the size distributions. In a next size correction quantity determining process (ST15), the size correction quantity of a design pattern of a photomask is determined according to the calculated mean value, so that the transfer pattern has specific design values.

公开(公告)号：JP2000155408A

公开(公告)日：2000-06-06

申请号：JP25170899

申请日：1999-09-06

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: H01L21/027 ,  G03F1/36 ,  G03F1/84 ,  G06F17/50 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To easily execute data certification of automatic light proximity effect software. SOLUTION: The data to be processed is inputted to a hierarchical structure processing section 11 where the hierarchical structure of the inputted data is subjected to an analysis and development processing. The processed data is then subjected to correction processing in a data correction processing section 12. At this time, the correction is executed by setting a correction quantity at zero. The data is transferred to an output data constitution section 13 where data output is executed. The output data outputted from this output data constitution section 13 and the input data are compared in a data comparison section 14. The comparison is made possible by the exclusive-OR processing of a pool function. The result of the exclusive-OR of the input data and the output data which is zero evidences that there are no problems in the data processing. The result which is 1 evidences that there is a problem in the data processing. If such certification method is used, the software is able to easily and rapidly execute the data certification when the hierarchical structure of the input data is subjected to the analysis and development processing.

公开(公告)号：JPH11111636A

公开(公告)日：1999-04-23

申请号：JP27238797

申请日：1997-10-06

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To prevent the occurrence of contamination which is caused by a metal sputtered from a silicide of the metal in an ion-implanting process in a semiconductor device manufacturing method. SOLUTION: On a semiconductor substrate 1, n-wells 6 and p-wells 7 are respectively formed in regions other than a region where a LOCOS oxide film 5 is formed, and a gate electrode 11 composed of a polysilicon film 9 and a WSi (tungsten silicide) film 10 is formed on each p-well 7 a gate oxide film 8 inbetween. Then, a thin film 20 composed of an organic compound is formed and a desired resist pattern 12 is formed. Then the source-drain region 13 of an n-channel transistor is formed in each p-well 7 by implanting As ions into the substrate 1. After the regions 13 have been formed, the resist pattern 12 and thin film 20A are removed. Then a BPSG film 15 having contact holes is formed, and a metal 16 for inter-layer connection and metallic wiring 17 are formed at the same time in the contact holes and on the BPSG film 15, respectively. In addition, a passivation film 18 is formed on the wiring 17.

公开(公告)号：JPH1144609A

公开(公告)日：1999-02-16

申请号：JP20273197

申请日：1997-07-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: G01M11/00 ,  G01M11/02

Abstract: PROBLEM TO BE SOLVED: To readily measure lens aberration of a projection aligner used for manufacturing semiconductor devices, etc. SOLUTION: A measurement pattern of this lens aberration comprises finer sub-patterns 12a, 12b than a main pattern 11 on both sides of the main pattern 11. In this case, a size of the sub-patterns 12a, 12b is near a resolution limit of this aligner, whereby an aberration amount of lens is measured by utilizing a fact that the two sub-patterns 12a, 12b indicate uneven image formation characteristics by the lens aberration.

公开(公告)号：JPH08298237A

公开(公告)日：1996-11-12

申请号：JP10286495

申请日：1995-04-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: G03F9/00 ,  H01L21/027

Abstract: PURPOSE: To enable the superposition measurement of a semiconductor device to be made high in accuracy and reproducibility. CONSTITUTION: A superposition measurement mark which serves as a mark for measuring the superposition of a first pattern on a second pattern in a semiconductor device manufacturing process is composed of an outer box mark 1 and an inner box mark 2, wherein one of the marks 1 and 2 is belt-like, and the other is square. Or, conductive material is embedded in a belt-like pattern and a square pattern.

公开(公告)号：JPH06224274A

公开(公告)日：1994-08-12

申请号：JP1073593

申请日：1993-01-26

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: H01L21/66

Abstract: PURPOSE:To easily detect a thin-film-like scum of about 30m thick by performing ion implantation on the conditions that the range be smaller than the film thickness of a resist scum, and after removing a photoresist to oxidize a substrate, detecting a difference in an interference color corresponding to the thickness of an oxide film. CONSTITUTION:A photoresist 2 is applied to the upper surface of a semiconductor substrate 1, exposed to light and developed to form a pattern, and after that, ion implantation is performed on the conditions that the range be smaller than the film thickness of a photoresist scum produced after the development of the resist 2 with respect to the substrate 1. Next, the photoresist is separated to oxidize the ion-implanted substrate 1, and then a difference in an interference color corresponding to the film thickness of the oxide films 7 to 9 between the part to be not ion-implanted due to the scum 3 and the parts 5, 6 to be ion-implanted is detected. For instance, a resist pattern is formed on a silicon substrate 1, and As ions 4 are implanted with acceleration energy of 20 KeV, and then the resist 2 is separated and then cleaned off to oxidize the substrate 1.

公开(公告)号：JPH05251539A

公开(公告)日：1993-09-28

申请号：JP4924192

申请日：1992-03-06

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/66

Abstract: PURPOSE:To optimize etching conditions from a result by observing a contact hole-forming state without damaging a silicon substrate itself. CONSTITUTION:In the case of etching to form a contact hole, it is first etched under standard conditions, an arbitrary contact hole 3 is sectional etched at a part 7 by using a focused ion beam, and a sectional shape of the hole, presence or absence of residue of an insulating film of a bottom 3a are observed. Propriety of etching conditions of the hole are decided according to the observed result.

公开(公告)号：JPH1050583A

公开(公告)日：1998-02-20

申请号：JP20801796

申请日：1996-08-07

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SAITO TAKU

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To accurately measure the superposing deviation between actual circuit patterns. SOLUTION: A first superposition measuring mark composed of a linear pattern having the same size as that of the design rule of a first circuit pattern, and a second superposition measuring mark 2 composed of a linear pattern having the same size as that of the design rule of a second circuit pattern are provided. The positional deviation between the first and second circuit patterns can be detected by detecting the positional difference between the marks 1 and 2 by using, for example, an optical superposing device. When the positional deviation is measured, the positional difference between image- forming positions hardly occurs at the time of exposure, and the superposing deviation between the actual circuit patterns can be measured accurately, because the marks 1 and 2 are composed of linear patterns having same sizes as those of the design rules of the actual circuit patterns.