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    SEMICONDUCTOR DEVICE
    1.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH08204118A

    公开(公告)日：1996-08-09

    申请号：JP1363295

    申请日：1995-01-31

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： SATO HISAHIRO ,  NOSE KOJI

    IPC: H01L23/12 ,  H01L23/02 ,  H01L25/04 ,  H01L25/18

    Abstract: PURPOSE: To prevent increase in the area of a semiconductor device and an increase in processing processes from being accompanied by forming the device into one chip by a method wherein inner leads are bonded to the main surface of a wiring chip and the electrode terminals of functional chips and the electrode terminals of the wiring chip and the electrode terminals of the wiring chip and the inner leads are respectively connected with each other via wires. CONSTITUTION: A plurality of functional chips 5 are connected with the main surface of a wiring chip 8 formed with a wiring and electrode terminals 6 of the chips 5 and electrode terminals 6 of the chip 8 and the terminals 6 of the chip 8 and inner leads 1 are respectively connected with each other via wires 9. The chips 5 are connected with the inner leads 1 via the chip 8. Accordingly, the connection of the wires 9 is prevented from being concentrated in each narrow range on the main surfaces of the chips 5 and an increase in a wiring impedance and an interference of signals between signal lines of dissimilar nodes are prevented from being generated. By fully improving the performances, such as operating speed, operating voltage margine and strength to electrostatic breaking, of a semiconductor chip, low power consumption and speedup of a semiconductor device can be obtained.

    REDUNDANT NON-VOLATILE MEMORY FOR RELIEVING
    5.
    发明专利
    REDUNDANT NON-VOLATILE MEMORY FOR RELIEVING 失效

    公开(公告)号：JPH07192493A

    公开(公告)日：1995-07-28

    申请号：JP33634193

    申请日：1993-12-28

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： SATO HISAHIRO ,  CHATANI SHIGEO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

    Abstract: PURPOSE:To obtain a redundant relieving circuit which prevents defect for cutting a fuse and can reduce a chip area, and a redundant non-volatile memory for relieving of a mask ROM. CONSTITUTION:Transistors DC20-DC35 for selecting a spare word line performs write-in corresponding to an address performing substitution by redundancy. When a threshold value is controlled and a gate potential of a transistor having a low threshold value is raised up, a current is made to flow from a drain to a source electrode, a potential of spare word lines by RWLO-RWLm is lowered. Only a word line selecting circuit which a gate potential of a transistor having a high threshold value is made to be at high level and a gate potential of a transistor having a low threshold value is made to be at a low level holds a potential of the spare word lines RWLO-RWLm at a high level.

    SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    7.
    发明专利
    SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH08329672A

    公开(公告)日：1996-12-13

    申请号：JP13035095

    申请日：1995-05-29

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： CHATANI SHIGEO ,  SATO HISAHIRO

    IPC: G11C14/00 ,  G11C11/401 ,  H01L27/10

    Abstract: PURPOSE: To enable a same circuit as RAM to be a ROM circuit by releasing the connection of a source electrode and capacity element of transistor(Tr) in a RAM circuit. CONSTITUTION: When this circuit and a memory cell are used as a mask ROM and data 0 is stored in a sense bus line BL1, a source electrode of the memory cell TrQ1 and a terminal of a storage capacity C1 are released. When reading out in this case, the TrQ1 and a dummy cell TrQ. 9 are switched on. But the potential of the bus line BL1 will remain unchanged because the source electrode of the TrQ1 is in an open state. On the other hand, TrQ9 becomes on, and the electric charges on the sense bus line/BL1 are distributed among the dummy cell capacitor C9 and the potential of the bus line/BL1 becomes lower than that of the sense bus BL1. Consequently, a column selection bus CL1 becomes high in the potential, TrQ5 and Q6 becomes on, a data line DQ becomes high, a data line/DQ become slow, and the data 0 can be fetched from a pair of the data lines.

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