公开(公告)号：JPH08288453A

公开(公告)日：1996-11-01

申请号：JP9046595

申请日：1995-04-17

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： CHATANI SHIGEO ,  SATOU HISAHIRO

IPC: H01L25/18 ,  H01L25/04

Abstract: PURPOSE: To reduce the cost and package size of a semiconductor device and, at the same time, to obtain a high development efficiency by reducing the number of bonding pads on a wiring board by directly connecting bonding pads on one semiconductor chip to bonding pads on another semiconductor chip through conductive wires. CONSTITUTION: Since bonding pads 14a on a first semiconductor chip 11 are directly connected to bonding pads 20 or 21 on a second or third semiconductor chip 12 or 13 through conductive wires 15, the number of bonding pads on a wiring board 16 and the size of the board 16 can be reduced. In addition, since the second or third chip 12 or 13 is directly connected to the first chip 11 through conductive wires 15, the chip size change of the second or third chip 12 or 13 can be coped with without redesigning the board 16 when the bonding pads 20 and 21 are positioned relatively to the first chip 11.

公开(公告)号：JPS5315082A

公开(公告)日：1978-02-10

申请号：JP8993076

申请日：1976-07-27

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SATOU HISAHIRO ,  ARITA SHIGERU ,  FURUTA MASAO ,  KAYAHARA MASAO

IPC: H03F1/52 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42

Abstract: PURPOSE:Application of a gate breakdown voltage to gates hence breakdown of the gates are prevented by adding a surface field control gate to each of protecting diodes.

公开(公告)号：JPS59218741A

公开(公告)日：1984-12-10

申请号：JP9273583

申请日：1983-05-26

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NOSE KOUJI ,  TANAKA SHIGERU ,  SATOU HISAHIRO

IPC: H01L21/52 ,  H01L21/58 ,  H05K3/34

Abstract: PURPOSE:To provide a solid state electronic device which preferably absorbs expansion difference between a solid state chip and its package base or a mounting substrate with less thermal deterioration and has stable quality and performance by bonding fixedly solid state chips at two positions with solders of different quality. CONSTITUTION:A capacitor chip 1 has electrodes 2, 3 at both ends, and is bonded fixedly with wiring electrodes 5, 6 of a ceramic package base 4 at both electrodes with conductive solder materials 7, 8 of different quality. The used solder material employs Au or Au-Si alloy for the material 7 and Sn-Ag alloy for the material 8. These solder materials are treated in nitrogen atmosphere or nitrogen and hydrogen mixture gas to be interposed between the electrodes for conductive bonding.

公开(公告)号：JPS586591A

公开(公告)日：1983-01-14

申请号：JP10415781

申请日：1981-07-02

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： SATOU HISAHIRO ,  HATSUTA MINORU

IPC: G11C17/00 ,  G11C17/12

Abstract: PURPOSE:To obtain a read only memory (ROM) with a high speed and less power consumption, by using a dummy cell and a sense amplifier for a semiconductor mask ROM and eliminating a current continuously flowing by utilizing a main circuit as dynamic circuits entirely. CONSTITUTION:A dummy cell of a semiconductor mask ROM consists of transistors (TRs) 31-33 and 46-48, and a memory cell comprises TRs 35-38, 40 and 42 having larger mutual conductance than that for the above, and the memory cells 34, 39, 41, 43-45 store the information opposite to the said memory cells. Bit lines 75-80 are charged with precharge circuits 61-63. One of word lines 68-71, ... is selected with column selection circuits 81 and 82, and when the line 69, for example, is selected, a dummy word line 72 is selected via sense amplifiers 64-66 consisting of dynamic circuits. Thus, the potential of the lines 78 and 79 is fast fallen down in comparison with the potential of the lines 75- 77, the potential of a line 80 is made to precharge state and read out to readout lines 73 and 74 via the TRs 49-54.

公开(公告)号：JPS57200993A

公开(公告)日：1982-12-09

申请号：JP8513981

申请日：1981-06-02

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OOSAWA AKIRA ,  SATOU HISAHIRO ,  FURUTA MASAO ,  IZUMI YOSHIHIRO

IPC: G11C17/00 ,  G11C11/40 ,  G11C29/00 ,  G11C29/44 ,  G11C29/56

Abstract: PURPOSE:To simplify a measurement of a storage holding characteristic, by measuring the storage holding quantity of a semiconductor nonvolatile memory being a body memory, A/D converting its result, and writing it in the second semiconductor nonvolatile memory. CONSTITUTION:A controlling circuit 4 operates a measuring circuit 3, and measures the storage holding quantity of a body memory 1. A result of its measurement is obtained as an output of the measuring circuit 3, and it is encoded by an A/D converting circuit 5 so as to be convenient for being written in a memory 2. This encoded measured value is written in the memory 2 by operation of the controlling circuit 4. Subsequently, the storage holding quantity of the body memory 1 is measured, and after that, read-out of the memory 2 is executed by the controlling circuit 4, and it is displayed on an indicator 6. Decision of the inspection is executed by the display of the indicator 6.

公开(公告)号：JPS5279670A

公开(公告)日：1977-07-04

申请号：JP15936275

申请日：1975-12-25

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FURUTA MASAO ,  SATOU HISAHIRO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To increase the rate of integration of non-volatile memory elements by selectively laminating an Si3N4 film on the SiO2 film selectively formed in the thickness at which tunneling can occur, thereby making a gate film.