公开(公告)号：US20180337766A1

公开(公告)日：2018-11-22

申请号：US15981269

申请日：2018-05-16

Applicant: MELEXIS TECHNOLOGIES NV

Inventor： Jörgen STURM ,  Thomas FREITAG ,  Martin BÖLTER ,  Anton BABUSHKIN

IPC: H04L7/00 ,  H04L12/40 ,  H04L12/12

CPC classification number: H04L7/0087 ,  H04L12/12 ,  H04L12/40 ,  H04L12/40039 ,  H04L2012/40215

Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.