METHOD FOR SUPERVISING AND INITIALIZING PORTS

    公开(公告)号:US20180336145A1

    公开(公告)日:2018-11-22

    申请号:US15974862

    申请日:2018-05-09

    Abstract: A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialisation signal comprising port initialisation data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialisation signal comprising the port initialisation data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialisation signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialisation data and the just obtained original one or more parity bits.

    DEVICE FOR SUPERVISING AND INITIALIZING PORTS

    公开(公告)号:US20180336102A1

    公开(公告)日:2018-11-22

    申请号:US15974784

    申请日:2018-05-09

    Abstract: A device for supervising ports of an integrated circuit is arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of the integrated circuit. The device comprises address decoding means, access control means, and parity controlling means. The device for supervising ports comprises read-back information means arranged for receiving input from the port and for passing that input to the parity control means and in that the address decoding means, the access control means, the read-back information means and the parity controlling means are arranged to be operative in a background loop wherein a range of port addresses is monitored. The read-back information means reads data and one or more parity bits stored on ports with an address in the range and the parity controlling means performs a parity check on the one or more parity bits stored on the ports.

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