公开(公告)号：DE69617893D1

公开(公告)日：2002-01-24

申请号：DE69617893

申请日：1996-07-17

Applicant: MICROCHIP TECH INC

Inventor： ALEXANDER E ,  HEWITT D

IPC: G11C16/06 ,  G11C7/10 ,  G11C8/04 ,  G11C16/20 ,  G11C16/26 ,  G11C7/00

Abstract: A sequential memory device having a read pipeline data structure for reading data from a bitline of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp for sensing the logic level appearing on the bitline, a flip-flop for providing an output signal indicative of the data bits received on the bitline, and means for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal.