公开(公告)号：JPH11224193A

公开(公告)日：1999-08-17

申请号：JP28565798

申请日：1998-10-07

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: PROBLEM TO BE SOLVED: To make selectable an addressing mode for every instruction by establishing a virtual register address set equivalent to many indirect addressing modes relating to an indirect addressing pointer inside a memory. SOLUTION: A data pointer register requires respective virtual register address positions inside a data memory for the respective indirect addressing modes desiring the realization of data pointer registers. The respective data pointer registers are provided with one or more reserved virtual register address positions inside a register address map. When the respective reserved virtual register address positions are accessed, the indirect addressing mode to the corresponding data pointer register is started. For instance, the respective data pointer registers which are the pointers of a 12-bit width capable of accessing the memory area of the length of 4K bytes are constituted as two 8-bit width registers accessible as readable and writable registers.

公开(公告)号：DE602006007551D1

公开(公告)日：2009-08-13

申请号：DE602006007551

申请日：2006-02-21

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  HU HARRY ,  SCHIEKE PIETER

IPC: H03M1/46 ,  H03M1/68 ,  H03M1/80

公开(公告)号：DE69804562T2

公开(公告)日：2002-11-21

申请号：DE69804562

申请日：1998-09-28

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

公开(公告)号：ES2154346T3

公开(公告)日：2001-04-01

申请号：ES95931545

申请日：1995-08-18

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K

IPC: G06F9/22 ,  G06F1/14 ,  G06F15/78 ,  G06F19/00

Abstract: A microcontroller chip with a central processing unit (CPU) is adapted to control an external system with which the device is to be installed in circuit. The microcontroller chip includes an on-chip peripheral universal timing function module with a register for storing a value selected to signify a distinctive event in a waveform. A timer generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register and the timer are coupled to a pin of the microcontroller chip on which said waveform is to be applied. Equality between the values in the timer and the register signify the distinctive event as one of a capture and a compare of an event in the waveform, to generate an interrupt to the CPU. The register is selectively split into separate master and slave registers for automatic synchronization of the transfer of a value entered into the master register to the slave register with a repetitive boundary of the waveform, to provide selective pulse width modulation of the waveform.

公开(公告)号：DE69807412D1

公开(公告)日：2002-10-02

申请号：DE69807412

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  MITRA SUMIT K

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：AT223082T

公开(公告)日：2002-09-15

申请号：AT98119376

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  MITRA SUMIT K

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：DE69807412T2

公开(公告)日：2003-04-17

申请号：DE69807412

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  MITRA SUMIT K

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：DE69804562D1

公开(公告)日：2002-05-08

申请号：DE69804562

申请日：1998-09-28

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

公开(公告)号：AT215713T

公开(公告)日：2002-04-15

申请号：AT98118314

申请日：1998-09-28

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

公开(公告)号：EP0728331A4

公开(公告)日：1997-05-07

申请号：EP95931545

申请日：1995-08-18

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K

IPC: G06F9/22 ,  G06F1/14 ,  G06F15/78 ,  G06F19/00

CPC classification number: G06F15/7814

Abstract: A microcontroller chip (10) controls an external system with which the device is installed and includes an on-chip peripheral universal timing function module (CCP1, CCP2) with a register (30) for storing a value selected to signify a distinctive event in a waveform. A timer (32) generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register (30) and timer (32) are coupled to a pin (33) of the microcontroller chip (10) on which said waveform is to be applied. Equality between the values in the timer (32) and the register (30) signify the event as one of a capture and a compare of an event in the waveform, to generate an interrupt to a CPU. The register (30) is selectively split into separate master (30-L) and slave (30-H) registers for automatic synchronization of the transfer of a value entered into the master register (30-L) to the slave register (30-H) with a repetitive boundary of the waveform, to provide selective pulse width modulation of the waveform.