公开(公告)号：JPH11232100A

公开(公告)日：1999-08-27

申请号：JP30756298

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  JOHANSEN DARREL ,  YACH RANDY L ,  BOLES BRIAN

IPC: G06F9/35

Abstract: PROBLEM TO BE SOLVED: To generate an indirect addressing mode address by providing a multiplexer circuit connected to the respective output terminals of a data pointer register, an incrementer and an adder. SOLUTION: A data pointer register 12 stores the current address of an operand used in a simple indirect addressing mode. An incrementer 14 increases the current address of the operand stored in the data pointer register 12. An adder 16 adds the current address and an offset value stored in the data pointer register 12. A multiplexer circuit 18 having a first input terminal connected to the output terminal of the data pointer register 12, a second input terminal connected to the output terminal of the incrementer 14 and a third input terminal connected to the output terminal of the adder 16 selects a desired generated indirect addressing mode address and outputs the selected address to an instruction register.

公开(公告)号：JPH11224192A

公开(公告)日：1999-08-17

申请号：JP30756098

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  YACH RANDY L ,  TRIECE JOSEPH W ,  CHIAO JENNIFER ,  WOJEWODA IGOR ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To increase a memory base capable of addressing by providing a second address bus for supplying all the address values of a two-word instruction to a linearized program memory in one cycle. SOLUTION: A first address bus 14 is connected to the linearized program memory 12 and is used for sending the address of a fetched instruction to the linearized program memory 12. A pointer 16 is connected to the first address bus 14. The second address bus 20 is provided with a first end part connected to the output of the linearized program memory 12 and the second end part of the second address bus 20 is connected to the first address bus 14. The second address bus 20 is used for arranging the address of the operand of the second word (word fetched during the execution of a first word) of the two-word instruction on the first address bus 14 after the address of the operand of the first word of the two-word instruction is arranged on the first address bus 14.

公开(公告)号：JPH11224193A

公开(公告)日：1999-08-17

申请号：JP28565798

申请日：1998-10-07

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: PROBLEM TO BE SOLVED: To make selectable an addressing mode for every instruction by establishing a virtual register address set equivalent to many indirect addressing modes relating to an indirect addressing pointer inside a memory. SOLUTION: A data pointer register requires respective virtual register address positions inside a data memory for the respective indirect addressing modes desiring the realization of data pointer registers. The respective data pointer registers are provided with one or more reserved virtual register address positions inside a register address map. When the respective reserved virtual register address positions are accessed, the indirect addressing mode to the corresponding data pointer register is started. For instance, the respective data pointer registers which are the pointers of a 12-bit width capable of accessing the memory area of the length of 4K bytes are constituted as two 8-bit width registers accessible as readable and writable registers.

公开(公告)号：JPH11212787A

公开(公告)日：1999-08-06

申请号：JP30613498

申请日：1998-10-27

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: PROBLEM TO BE SOLVED: To maximize the number of usable operation codes and addressable registers and also to enable a multiple addressing mode by having an instruction set which can realize an addressing mode in which plural instructions are different from each other. SOLUTION: An instruction 30 includes plural bits 32. The bits 32 are divided into an operation code field 34 that shows what type of an operation is performed, a destination bit 36 that shows where operation results are stored and a register address field 38 which shows a register where the instruction 30 is operated or the address of variable data. The lengths of the fields 34 and 38 are determined by the number of operation codes a user desires to realize or the number of addressable registers. Virtual register address positions in a processor architecture system used together with the instruction 30 respectively start an indirect addressing mode when they are accessed.

公开(公告)号：JP2000330968A

公开(公告)日：2000-11-30

申请号：JP2000108694

申请日：2000-04-10

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  BOLES EDWARD BRIAN ,  DRAKE RODNEY

IPC: G06F15/78 ,  G06F9/50 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To simultaneously use two pieces of different peripheral equipment capable of functioning by a single pin by providing process circuit mechanism and settable pin setting. SOLUTION: A multiplexer 14 is connected with a function circuit 12 via a communication line 18, connected with a pin P1 via a communication line 20, connected with a pin P2 via a communication line 22 and connected with a setting register 16 via a communication line 24. When a flag received from the setting register 16 is '1', the multiplexer 14 is operated so as to connect the function circuit 12 with the pin P1. When the flag received from the setting register 16 is 'zero', the multiplexer 14 is further operated so as to connect the function circuit 12 with the pin P2. Therefore, a user is able to transfer a function related to the function circuit 12 from one pin to another by using the multiplexer 14 and the setting register 16 by a circuit 10.

公开(公告)号：JPH11191066A

公开(公告)日：1999-07-13

申请号：JP27616598

申请日：1998-09-29

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To obtain an instruction set that is improved by a microcontroller by arranging one bit of a multiple work instruction of an instruction set at a position in the entire non-leading word and decoding it as no operation bit when a leading word of the multiple word instruction is not first carried out. SOLUTION: In each multiple work instruction 2 and 3, at least one no- operation bit 18 is arranged at a prescribed position in each non-leading word 14B to 14N. When a leading word 14A is not executed before a word that follows it in a multiple word instruction, each non-leading word 14B to 14N of the multiple word instructions is recognized as a non-operation word by the bit 18. Then, in an instruction 3, if the word 14A is not carried out before a 2nd word 14B or N-th word 14N when a microcontroller jumps in the word 14B or the word 14N in the instruction carelessly, the microcontroller decodes each non-leading word 14B to 14N as no operation word.

公开(公告)号：WO2013085992A3

公开(公告)日：2014-02-06

申请号：PCT/US2012067944

申请日：2012-12-05

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  TRIECE JOSEPH W ,  ROGERS CLARK J ,  SCHIEKE PIETER

IPC: H02M3/156 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H02M2001/0045

Abstract: An integrated circuit device has a digital device (600) operating at an internal core voltage (Vint); a linear voltage regulator (510); and an internal switched mode voltage regulator (180) controlled by the digital device and receiving an external supply voltage (Vext) being higher than the internal core voltage through at least first and second external pins (140a, 140b) and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component (182) through at least one further external pin (140c) of the plurality of external pins.

Abstract translation: 集成电路装置具有以内部核心电压（Vint）工作的数字装置（600）; 线性稳压器（510）; 和由数字装置控制的内部开关模式电压调节器（180），并通过至少第一和第二外部引脚（140a，140b）接收高于内部核心电压的外部电源电压（Vext），并产生内部核心电压 ，其中所述内部开关模式电压调节器通过所述多个外部引脚的至少一个另外的外部引脚（140c）与至少一个外部部件（182）耦合。

公开(公告)号：DE69808020T2

公开(公告)日：2003-05-22

申请号：DE69808020

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  YACH RANDY L ,  BOLES BRIAN ,  WOJEWODA IGOR ,  JOHANSEN DARREL

IPC: G06F9/35

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

公开(公告)号：DE60000296T2

公开(公告)日：2003-04-17

申请号：DE60000296

申请日：2000-04-07

Applicant: MICROCHIP TECH INC

Inventor： BOLES EDWARD BRIAN ,  DRAKE RODNEY J ,  TRIECE JOSEPH W

IPC: G06F15/78 ,  G06F9/50 ,  G06F13/40

公开(公告)号：AU2002331006A1

公开(公告)日：2003-03-03

申请号：AU2002331006

申请日：2002-08-07

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W

IPC: G06F1/32 ,  G06F11/26 ,  G06F11/36

Abstract: A microprocessor comprises a central processing unit receiving a first clock signal, a plurality of peripherals receiving a second clock signal a first select unit for selecting the first clock signal out of a plurality of clock signals and a second select unit for selecting the second clock signal out of the plurality of clock signals. The central processing unit comprises an execution unit which controls the select units upon execution of a low power mode instruction to select a clock signal for the central processing unit and the peripheral units.