公开(公告)号：AT384291T

公开(公告)日：2008-02-15

申请号：AT05754513

申请日：2005-05-26

Applicant: MICROCHIP TECH INC

Inventor： JULICHER JOSEPH ,  OTTEN DAVID ,  BUTLER DANIEL

IPC: G06F1/08 ,  G06F1/26 ,  H03L7/06

Abstract: Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an integer multiple of a reference oscillator. The clock speed will be proportional to the frequency multiplication of the PLL when the faster clock speed is selected. A multiplexer is used to switch between different frequency sources, and a timer can be used to insure stable operation of the PLL. A status configuration register has status and control bits for indicating and controlling operation of the clock speed control. A universal serial bus (USB) device can operate at a slower clock with reduced operating voltage, and at a faster clock with increased operating voltage.