公开(公告)号：DE69829649T2

公开(公告)日：2006-02-02

申请号：DE69829649

申请日：1998-12-16

Applicant: MICROCHIP TECH INC

Inventor： THOMSEN A ,  PHOENIX J ,  BOLES BRIAN ,  PENA HENRY ,  LUKE E

IPC: G11C16/02 ,  G11C8/12 ,  G11C16/00 ,  G11C16/16

Abstract: An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.

公开(公告)号：DE69829649D1

公开(公告)日：2005-05-12

申请号：DE69829649

申请日：1998-12-16

Applicant: MICROCHIP TECH INC

Inventor： THOMSEN A ,  PHOENIX J ,  BOLES BRIAN ,  PENA HENRY ,  LUKE E

IPC: G11C16/02 ,  G11C8/12 ,  G11C16/16 ,  G11C16/00

Abstract: An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.