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    DATA POINTER TO OUTPUT INDIRECT ADDRESSING MODE ADDRESS WITHIN SINGLE CYCLE AND ITS METHOD
    1.
    发明专利
    DATA POINTER TO OUTPUT INDIRECT ADDRESSING MODE ADDRESS WITHIN SINGLE CYCLE AND ITS METHOD 失效

    公开(公告)号：JPH11232100A

    公开(公告)日：1999-08-27

    申请号：JP30756298

    申请日：1998-10-28

    Applicant: MICROCHIP TECH INC

    Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  JOHANSEN DARREL ,  YACH RANDY L ,  BOLES BRIAN

    IPC: G06F9/35

    Abstract: PROBLEM TO BE SOLVED: To generate an indirect addressing mode address by providing a multiplexer circuit connected to the respective output terminals of a data pointer register, an incrementer and an adder. SOLUTION: A data pointer register 12 stores the current address of an operand used in a simple indirect addressing mode. An incrementer 14 increases the current address of the operand stored in the data pointer register 12. An adder 16 adds the current address and an offset value stored in the data pointer register 12. A multiplexer circuit 18 having a first input terminal connected to the output terminal of the data pointer register 12, a second input terminal connected to the output terminal of the incrementer 14 and a third input terminal connected to the output terminal of the adder 16 selects a desired generated indirect addressing mode address and outputs the selected address to an instruction register.

    2.
    发明专利
    未知

    公开(公告)号：AT506749T

    公开(公告)日：2011-05-15

    申请号：AT07762367

    申请日：2007-05-31

    Applicant: MICROCHIP TECH INC

    Inventor： WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

    IPC: H03K19/0175

    Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

    4.
    发明专利
    未知

    公开(公告)号：DE69808020D1

    公开(公告)日：2002-10-24

    申请号：DE69808020

    申请日：1998-10-14

    Applicant: MICROCHIP TECH INC

    Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  YACH RANDY L ,  BOLES BRIAN ,  WOJEWODA IGOR ,  JOHANSEN DARREL

    IPC: G06F9/35

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    6.
    发明专利
    未知

    公开(公告)号：DE69829649D1

    公开(公告)日：2005-05-12

    申请号：DE69829649

    申请日：1998-12-16

    Applicant: MICROCHIP TECH INC

    Inventor： THOMSEN A ,  PHOENIX J ,  BOLES BRIAN ,  PENA HENRY ,  LUKE E

    IPC: G11C16/02 ,  G11C8/12 ,  G11C16/16 ,  G11C16/00

    Abstract: An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.

    PERIPHERAL SUPPLIED ADDRESSING IN A SIMPLE DMA
    7.
    发明申请
    PERIPHERAL SUPPLIED ADDRESSING IN A SIMPLE DMA 审中-公开
    外部提供简单的DMA寻址

    公开(公告)号：WO2008014244A2

    公开(公告)日：2008-01-31

    申请号：PCT/US2007074194

    申请日：2007-07-24

    Applicant: MICROCHIP TECH INC ,  SMIT MARIA ,  DAWSON STEVEN ,  BOLES BRIAN

    Inventor： DAWSON STEVEN ,  BOLES BRIAN ,  SMIT WILLEM

    CPC classification number: G06F13/28

    Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

    Abstract translation: 执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。

    DYNAMIC PERIPHERAL FUNCTION REMAPPING TO EXTERNAL INPUT-OUTPUT CONNECTIONS OF AN INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    DYNAMIC PERIPHERAL FUNCTION REMAPPING TO EXTERNAL INPUT-OUTPUT CONNECTIONS OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
    一体化电路设备的外部输入输出连接的动态外设功能

    公开(公告)号：WO2007143494A3

    公开(公告)日：2008-03-13

    申请号：PCT/US2007070066

    申请日：2007-05-31

    Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

    Inventor： WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

    IPC: H03K19/0175

    CPC classification number: H03K19/17764 ,  H03K19/1732 ,  H03K19/17744

    Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input- output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

    Abstract translation: 通过使用一组配置寄存器，集成电路设备的外围功能可以被集合并且动态地映射到集成电路设备的可用的外部输入 - 输出连接。 为了提供系统的鲁棒性，配置寄存器可以实现各种级别的写保护，纠错和监视电路。 一个或多个外围输出功能可以映射到一个或多个外部输出连接。 在同一输出连接上，同一输出功能可能同时处于活动状态。 输出和输入可以被映射到相同的外部输入 - 输出连接，具有或不具有可控制的输出以放置到非活动状态，例如高阻抗或开路集电极。 当输入需要通过外部输入 - 输出连接接收外部数据时，输出可能被置于非活动状态。

    10.
    发明专利
    未知

    公开(公告)号：DE69829649T2

    公开(公告)日：2006-02-02

    申请号：DE69829649

    申请日：1998-12-16

    Applicant: MICROCHIP TECH INC

    Inventor： THOMSEN A ,  PHOENIX J ,  BOLES BRIAN ,  PENA HENRY ,  LUKE E

    IPC: G11C16/02 ,  G11C8/12 ,  G11C16/00 ,  G11C16/16

    Abstract: An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.

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