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1.发明授权
公开(公告)号：EP0783755B1
公开(公告)日：2001-12-12
申请号：EP96924423.5
申请日：1996-07-17
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： ALEXANDER, Samuel, E. , HEWITT, Kent, D.
IPC: G11C7/00
CPC classification number: G11C7/106 , G11C7/1039 , G11C7/1051 , G11C8/04 , G11C16/20 , G11C16/26
Abstract: A sequential memory device (10) having a read pipeline data structure for reading data from a bitline (32, 33) of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp (40, 40') for sensing the logic level appearing on the bitline (32, 33), and a flip-flop (46, 46') for providing an output signal indicative of the data bits received on the bitline (32, 32'), and means (101) for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal (CLK).
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2.发明公开INDEPENDENTLY PROGRAMMABLE MEMORY SEGMENTS IN ISOLATED N-WELLS WITHIN A PMOS EEPROM ARRAY AND METHOD THEREFOR 有权一个PMOS EEPROM器件内的隔离的N阱可独立编程的存储器区段的制造方法
公开(公告)号：EP1090425A1
公开(公告)日：2001-04-11
申请号：EP00918141.3
申请日：2000-03-17
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： GERBER, Donald, S. , YACH, Randy, L. , HEWITT, Kent, D. , SPADINI, Gianpaolo
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.
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3.发明公开
公开(公告)号：EP0783755A1
公开(公告)日：1997-07-16
申请号：EP96924423.0
申请日：1996-07-17
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： ALEXANDER, Samuel, E. , HEWITT, Kent, D.
CPC classification number: G11C7/106 , G11C7/1039 , G11C7/1051 , G11C8/04 , G11C16/20 , G11C16/26
Abstract: A sequential memory device (10) having a read pipeline data structure for reading data from a bitline (32, 33) of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp (40, 40') for sensing the logic level appearing on the bitline (32, 33), and a flip-flop (46, 46') for providing an output signal indicative of the data bits received on the bitline (32, 32'), and means (101) for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal (CLK).
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4.发明授权Methods of forming independently programmable memory segments in isolated N-wells within a PMOS EEPROM device 有权一个PMOS EEPROM器件内的隔离的N阱可独立编程的存储器区段的制造方法
公开(公告)号：EP1090425B1
公开(公告)日：2012-06-27
申请号：EP00918141.3
申请日：2000-03-17
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： GERBER, Donald, S. , YACH, Randy, L. , HEWITT, Kent, D. , SPADINI, Gianpaolo
IPC: H01L27/115 , H01L21/8247 , G11C16/04 , H01L27/02
CPC classification number: H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.
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