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    MEMORY DEVICE PROCESSING
    1.
    发明申请
    MEMORY DEVICE PROCESSING 审中-公开

    公开(公告)号：WO2020081193A1

    公开(公告)日：2020-04-23

    申请号：PCT/US2019/052365

    申请日：2019-09-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： FINKBEINER, Timothy P. ,  LARSEN, Troy D.

    IPC: G11C11/4091 ,  G11C8/12 ,  G11C11/408 ,  G06F3/06

    Abstract: Embodiments described herein include apparatuses and methods for memory device processing. More specifically, an example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks. The processing -in-memory device of the example apparatus may save time and/or power by reducing and/or eliminating external communications.

    VECTOR REGISTERS IMPLEMENTED IN MEMORY
    7.
    发明申请
    VECTOR REGISTERS IMPLEMENTED IN MEMORY 审中-公开

    公开(公告)号：WO2020077020A1

    公开(公告)日：2020-04-16

    申请号：PCT/US2019/055487

    申请日：2019-10-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： FINKBEINER, Timothy P. ,  LARSEN, Troy D.

    IPC: G06F9/30 ,  G06F12/02

    Abstract: Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.

    COHERENT MEMORY ACCESS
    8.
    发明申请
    COHERENT MEMORY ACCESS 审中-公开

    公开(公告)号：WO2020076831A1

    公开(公告)日：2020-04-16

    申请号：PCT/US2019/055200

    申请日：2019-10-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： FINKBEINER, Timothy P. ,  LARSEN, Troy D.

    IPC: G06F12/0831 ,  G06F12/0844 ,  G06F12/0866 ,  G06F12/0875

    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

    DATA COMPRESSION AND MANAGEMENT
    9.
    发明申请
    DATA COMPRESSION AND MANAGEMENT 审中-公开
    数据压缩与管理

    公开(公告)号：WO2013192548A1

    公开(公告)日：2013-12-27

    申请号：PCT/US2013/047107

    申请日：2013-06-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MANNING, Troy A. ,  LARSEN, Troy D. ,  CULLEY, Martin L. ,  MEADER, Jeffrey L. ,  BARD, Steve G. ,  EYRES, Dean C.

    IPC: G06F12/00

    CPC classification number: G06F3/0608 ,  G06F3/0661 ,  G06F3/0673 ,  H03M7/30 ,  H03M7/60 ,  H03M7/6082

    Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

    Abstract translation: 本公开包括用于数据压缩和管理的装置和方法。 多种方法包括接收与被管理单元数据量相对应的多个数据段，确定每个数据段的相应可压缩性，根据其各自确定的可压缩性来压缩每个数据段的数目，形成 压缩的被管理单元，其包括对应于与被管理单元数据量相对应的数据段的数量的压缩和/或未压缩的数据段，以及形成至少包括压缩的被管理单元的数据页。

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