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    APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY
    1.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY 审中-公开
    使用感应电路执行比较操作的装置和方法

    公开(公告)号：WO2015013043A1

    公开(公告)日：2015-01-29

    申请号：PCT/US2014/046094

    申请日：2014-07-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MANNING, Troy A.

    IPC: G11C7/06 ,  G11C7/10

    CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

    Abstract translation: 本公开包括与使用感测电路执行比较和/或报告操作相关的装置和方法。 示例性方法可以包括将存储器阵列的输入/输出（IO）线充电到电压。 该方法可以包括确定存储在存储器阵列中的数据是否与比较值相匹配。 确定存储的数据是否与比较值匹配可以包括激活存储器阵列的多个访问线。 该确定可以包括感测耦合到接入线路数量的多个存储器单元。 该确定可以包括检测IO线的电压是否响应于对应于存储器单元的数量的所选择的解码线的激活而改变。

    INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES
    2.
    发明申请
    INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES 审中-公开
    独立可寻址的内存阵列地址空间

    公开(公告)号：WO2015031051A1

    公开(公告)日：2015-03-05

    申请号：PCT/US2014/050816

    申请日：2014-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MANNING, Troy A.

    IPC: G11C15/00

    CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

    Abstract translation: 本公开的示例提供用于访问存储器阵列地址空间的设备和方法。 一种示例性存储器阵列，其包括第一地址空间，该第一地址空间包括耦合到第一数量的选择线和多条感测线的存储器单元，以及包括耦合到第二数量的选择线的存储器单元和感测线的数量的第二地址空间 。 第一地址空间相对于第二地址空间可独立地寻址。

    DATA COMPRESSION AND MANAGEMENT
    3.
    发明申请
    DATA COMPRESSION AND MANAGEMENT 审中-公开
    数据压缩与管理

    公开(公告)号：WO2013192548A1

    公开(公告)日：2013-12-27

    申请号：PCT/US2013/047107

    申请日：2013-06-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MANNING, Troy A. ,  LARSEN, Troy D. ,  CULLEY, Martin L. ,  MEADER, Jeffrey L. ,  BARD, Steve G. ,  EYRES, Dean C.

    IPC: G06F12/00

    CPC classification number: G06F3/0608 ,  G06F3/0661 ,  G06F3/0673 ,  H03M7/30 ,  H03M7/60 ,  H03M7/6082

    Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

    Abstract translation: 本公开包括用于数据压缩和管理的装置和方法。 多种方法包括接收与被管理单元数据量相对应的多个数据段，确定每个数据段的相应可压缩性，根据其各自确定的可压缩性来压缩每个数据段的数目，形成 压缩的被管理单元，其包括对应于与被管理单元数据量相对应的数据段的数量的压缩和/或未压缩的数据段，以及形成至少包括压缩的被管理单元的数据页。

    MEMORY MAPPING
    5.
    发明申请
    MEMORY MAPPING 审中-公开
    记忆映射

    公开(公告)号：WO2015142806A1

    公开(公告)日：2015-09-24

    申请号：PCT/US2015/020903

    申请日：2015-03-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MURPHY, Richard C. ,  MANNING, Troy A.

    IPC: G06F12/06 ,  G06F12/02

    CPC classification number: G11C29/18 ,  G11C29/44 ,  G11C2029/1806 ,  G11C2029/4402

    Abstract: The present disclosure includes apparatuses, electronic device readable media, and methods for memory mapping. One example method can include testing a memory identifier against an indication corresponding to a set of mapped memory identifiers, and determining a memory location corresponding to the memory identifier responsive to testing.

    Abstract translation: 本公开包括设备，电子设备可读介质和用于存储器映射的方法。 一个示例性方法可以包括针对与映射的存储器标识符的集合相对应的指示来测试存储器标识符，以及响应于测试来确定与存储器标识符相对应的存储器位置。

    LOGICAL OPERATIONS USING MEMORY CELLS
    9.
    发明申请
    LOGICAL OPERATIONS USING MEMORY CELLS 审中-公开

    公开(公告)号：WO2019152189A1

    公开(公告)日：2019-08-08

    申请号：PCT/US2019/013765

    申请日：2019-01-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MANNING, Troy A. ,  HUSH, Glen E.

    IPC: G11C11/4093 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

    APPARATUSES AND METHODS FOR PERFORMING AN EXCLUSIVE OR OPERATION USING SENSING CIRCUITRY
    10.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING AN EXCLUSIVE OR OPERATION USING SENSING CIRCUITRY 审中-公开
    使用感应电路执行独占或操作的装置和方法

    公开(公告)号：WO2015187771A2

    公开(公告)日：2015-12-10

    申请号：PCT/US2015/033889

    申请日：2015-06-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MANNING, Troy A.

    CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/42

    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

    Abstract translation: 本公开包括与确定存储器中的异或值相关的装置和方法。 示例性方法可以包括对存储在第一存储器单元中的数据值和存储在第二存储器单元中的数据值执行NAND操作。 该方法可以包括对存储在第一和第二存储器单元中的数据值执行或运算。 该方法可以包括对NAND操作的结果执行AND运算和OR运算的结果，而不经由输入/输出（I / O）线从存储器阵列传送数据。

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