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    A CONSTANT PULSE WIDTH GENERATOR
    1.
    发明专利
    A CONSTANT PULSE WIDTH GENERATOR 未知

    公开(公告)号：MY163408A

    公开(公告)日：2017-09-15

    申请号：MYPI2012701209

    申请日：2012-12-18

    Applicant: MIMOS BERHAD

    Inventor： HANIF CHE LAH ,  WEE LEONG SON ,  ROZITA BORHAN

    IPC: H03K3/017 ,  H03K5/156

    Abstract: THE PRESENT INVENTION GENERALLY PERTAINS TO A PULSE GENERATOR (100) AND A METHOD FOR PRODUCING PULSE, MORE PARTICULARLY THE PRESENT INVENTION PERTAINS TO A CONSTANT PULSE WIDTH GENERATOR AND A METHOD FOR PRODUCING CONSTANT PULSE WIDTH SIGNALS, WHEREIN THE PULSE GENERATOR (100) COMPRISES AN INPUT (11) FOR RECEIVING SIGNALS, A SIGNAL DETECTOR (12) FOR DETECTING SIGNAL LEVELS, A FREQUENCY DIVIDER (13) FOR DIVIDING FREQUENCY OF THE SIGNALS, AT LEAST A SIGNAL GENERATOR (14) FOR GENERATING PREDETERMINED PULSE WIDTH SIGNALS FROM THE FREQUENCY DIVIDED SIGNALS, AT LEAST AN INTEGRATOR (15) FOR INTEGRATING THE SIGNALS, AND AT LEAST AN OUTPUT (16) FOR PROVIDING CONSTANT PULSE WIDTH SIGNALS. MOST ILLUSTRATIVE DRAWING:

    METHOD AND SYSTEM FOR TRANSFERRING DATA THROUGH TWO DIFFERENT CLOCK DOMAINS
    2.
    发明专利
    METHOD AND SYSTEM FOR TRANSFERRING DATA THROUGH TWO DIFFERENT CLOCK DOMAINS 未知

    公开(公告)号：MY171066A

    公开(公告)日：2019-09-24

    申请号：MYPI2014003297

    申请日：2014-11-25

    Applicant: MIMOS BERHAD

    Inventor： ROZITA BORHAN ,  WEE LEONG SON ,  MUHAMAD KHAIROL BIN AB RANI

    Abstract: [0030] There is disclosed a system for transferring data between two asynchronous clock domains, thus having at least a source clock (first clock domain) and a receiving clock (second clock domain); the system comprising: a multiplexer (20) for providing the first input; a register (30, 90) configured for receiving and storing data input at the first clock domain (1) and second clock domain (2); a comparison module (40,70) at the first clock domain (1) and second clock domains (2) configured for receiving incoming data input comparing data inputs; a controller (50, 80) at the first clock domain (1) and second clock domain (2) configured to receive the comparison output and toggling at least one signal (in2out) if a data change is detected based on the comparison; at least one synchronizer (60) to synchronizes signals into the second clock domain (2).

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