公开(公告)号：BR0204679A

公开(公告)日：2003-04-08

申请号：BR0204679

申请日：2002-03-05

Applicant: MOTOROLA INC

Inventor： RINDERKNECHT WILLIAM J ,  SCHOOLER ANTHONY ,  ANDREWS KEVIN M ,  KIM YUN

IPC: H04L7/00 ,  H04L7/02

Abstract: A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.

公开(公告)号：EP0720734A4

公开(公告)日：1997-07-23

申请号：EP95918407

申请日：1995-05-08

Applicant: MOTOROLA INC

Inventor： HUNNINGHAUS ROY E ,  MURPHY PETER W ,  ANDREWS KEVIN M

IPC: G01L23/22

CPC classification number: G01L23/225

Abstract: A knock detection method and apparatus integrates a knock sensor signal (107) over a first period and provides a first integrated knock sensor signal (119), and integrates the knock sensor signal (107) over a second period and provides a second integrated knock sensor signal (139). A knock indication (131) is provided dependent on an amplitude of the first integrated knock sensor signal (119) and an amplitude of the second integrated knock sensor signal (139).

公开(公告)号：EP1374471A4

公开(公告)日：2006-05-24

申请号：EP02719118

申请日：2002-03-05

Applicant: MOTOROLA INC

Inventor： RINDERKNECHT WILLIAM J ,  SCHOOLER ANTHONY ,  ANDREWS KEVIN M ,  KIM YUN

IPC: H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0029 ,  H03H17/0286 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0245 ,  H03H2218/12

Abstract: A method for performing timing synchronization (fig. 3) between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate (34) and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting (36 and 38) the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.

公开(公告)号：EP0890297A4

公开(公告)日：2001-04-11

申请号：EP97939598

申请日：1997-08-27

Applicant: MOTOROLA INC

Inventor： HUNNINGHAUS ROY E ,  ANDREWS KEVIN M ,  CHRISTOPHER GARY L ,  ANDERSON DAVID J ,  TOMASE JOSEPH P

IPC: H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K3/34 ,  H05K3/42 ,  H05K7/20 ,  H05K1/00 ,  H01L23/34

CPC classification number: H05K7/20509 ,  H05K1/0206 ,  H05K3/0061 ,  H05K3/341 ,  H05K3/42 ,  H05K2201/066 ,  H05K2201/10166 ,  H05K2201/10969

Abstract: An electronic control module (10) includes a circuit substrate (12) containing a plurality of thermal vias (36) and a heat-generating electronic device (26) attached to the thermal vias (36). The circuit substrate (12) is attached to a mounting plate (18) by a plurality of electrically-isolated, thermal attachment pads (20) located at selected positions on an electrically insulating layer (16) overlying a metal baseplate (14). A solder layer (22) functions to both mechanically attach the plurality of thermal vias (36) to the plurality of thermal attachment pads (20), and to provide a thermal dissipation pathway for heat generated by the electronic devices (26). The heat is transferred from the circuit substrate (12) through the plurality of thermal attachment pads (20) to the metal baseplate (14).