Abstract:
The invention provides a method for generating a code sequence. A code-generation instruction is received from memory. One or more control signals are determined based on the code-generation instruction. A code sequence is generated based on the control signals, a current state input, and a mask input.
Abstract:
An apparatus and method of filtering at least one set of data comprises determining a subset of Q data elements of a set of L data elements (12), and determining a filtered value based upon the subset of Q data elements (14). Each of the subset of Q data elements is greater than at most a first predetermined number of the L data elements and greater than or equal to at least a second predetermined number of the L data elements other than itself.
Abstract:
An apparatus and method of filtering at least one set of data comprises determining a subset of Q data elements of a set of L data elements (12), and determining a filtered value based upon the subset of Q data elements (14). Each of the subset of Q data elements is greater than at most a first predetermined number of the L data elements and greater than or equal to at least a second predetermined number of the L data elements other than itself.
Abstract:
An apparatus and method of filtering at least one set of data comprises determining a subset of Q data elements of a set of L data elements (12), and determining a filtered value based upon the subset of Q data elements (14). Each of the subset of Q data elements is greater than at most a first predetermined number of the L data elements and greater than or equal to at least a second predetermined number of the L data elements other than itself.
Abstract:
A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.
Abstract:
A method for performing timing synchronization (fig. 3) between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate (34) and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting (36 and 38) the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.
Abstract:
An apparatus and method of filtering at least one set of data comprises determining a subset of Q data elements of a set of L data elements (12), and determining a filtered value based upon the subset of Q data elements (14). Each of the subset of Q data elements is greater than at most a first predetermined number of the L data elements and greater than or equal to at least a second predetermined number of the L data elements other than itself.