公开(公告)号：AU2002359626A1

公开(公告)日：2003-07-24

申请号：AU2002359626

申请日：2002-11-21

Applicant: MOTOROLA INC

Inventor： KIM YUN ,  RINCERKNECHT WILLIAM JOHN ,  YE ZHUAN ,  CHAU BENSON ,  SCHOOLER ANTHONY ,  GURNEY DAVID P

IPC: H04B1/7075 ,  H04J11/00 ,  H04J13/00 ,  H04J13/10 ,  H04L17/18

Abstract: The invention provides a method for generating a code sequence. A code-generation instruction is received from memory. One or more control signals are determined based on the code-generation instruction. A code sequence is generated based on the control signals, a current state input, and a mask input.

公开(公告)号：AU2003223290A1

公开(公告)日：2003-11-10

申请号：AU2003223290

申请日：2003-03-17

Applicant: MOTOROLA INC

Inventor： GURNEY DAVID P ,  SCHOOLER ANTHONY R ,  YE ZHUAN ,  KIM YUN

IPC: H04B1/709 ,  G06F17/15 ,  H04B7/08 ,  H04L27/30

Abstract: A programmable correlator for a communication system includes an input queue coupled with an analog-to-digital converter (ADC). The input queue includes a random access memory (RAM) wherein sampled data streams from the ADC are written into the RAM. The input queue has two banks of memory of width 2M. A flexible complex correlator is operable on M samples. The correlator is coupled to read M complex samples out of 2M samples from the input queue. A pseudo-noise (PN) crossbar unit operates to rotate a generated PN code to match a rotation of the input queue data in the complex correlator.

公开(公告)号：BR0204679A

公开(公告)日：2003-04-08

申请号：BR0204679

申请日：2002-03-05

Applicant: MOTOROLA INC

Inventor： RINDERKNECHT WILLIAM J ,  SCHOOLER ANTHONY ,  ANDREWS KEVIN M ,  KIM YUN

IPC: H04L7/00 ,  H04L7/02

Abstract: A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.

公开(公告)号：EP1374471A4

公开(公告)日：2006-05-24

申请号：EP02719118

申请日：2002-03-05

Applicant: MOTOROLA INC

Inventor： RINDERKNECHT WILLIAM J ,  SCHOOLER ANTHONY ,  ANDREWS KEVIN M ,  KIM YUN

IPC: H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0029 ,  H03H17/0286 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0245 ,  H03H2218/12

Abstract: A method for performing timing synchronization (fig. 3) between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate (34) and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting (36 and 38) the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.