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    Insulated gate field-effect device and method of fabrication
    4.
    发明授权
    Insulated gate field-effect device and method of fabrication 失效
    绝缘栅场效应器件及制造方法

    公开(公告)号：US3696276A

    公开(公告)日：1972-10-03

    申请号：US3696276D

    申请日：1970-06-05

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W

    IPC: H01L21/316 ,  H01L23/29 ,  H01L29/00 ,  H01L11/14

    CPC classification number: H01L23/291 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/31662 ,  H01L23/29 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/13091 ,  Y10S148/043 ,  Y10S148/049 ,  Y10S148/053 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/118 ,  H01L2924/00

    Abstract: An insulated gate field-effect transistor is fabricated to include an improved insulation layer comprising a film of silicon dioxide covered with a film of silicon nitride. The method of fabrication includes the thermal oxidation of a semiconductor silicon surface in a ''''reducing'''' atomsphere. The use of hydrogen as a carrier gas for oxygen provides a thermally grown, pinholefree oxide film having improved stability under conditions of heat cycling and electrical bias. The process permits a control of oxidation rate by adjusting the oxygen content of the gaseous mixture, rather than by the control of temperature. Best device characteristics are obtained by proceeding immediately with the vapor deposition of silicon nitride on the oxide, as a substantially continuous operation in the same reactor.

    Abstract translation: 绝缘栅场效应晶体管被制造成包括改进的绝缘层，其包括用氮化硅膜覆盖的二氧化硅膜。 制造方法包括在“还原”原子层中半导体硅表面的热氧化。 使用氢气作为氧气的载气提供了热生长的无针孔氧化膜，其在热循环和电偏压的条件下具有改进的稳定性。 该方法允许通过调节气体混合物的氧含量而不是通过控制温度来控制氧化速率。 通过在氧化物上气相沉积氮化硅，在同一反应器中作为基本连续的操作，可以获得最佳的器件特性。

    7.
    发明专利
    未知

    公开(公告)号：DE3484708D1

    公开(公告)日：1991-07-18

    申请号：DE3484708

    申请日：1984-11-15

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W

    IPC: H01L21/8222 ,  H01L21/20 ,  H01L21/76 ,  H01L21/761 ,  H01L27/06 ,  H01L27/08

    Abstract: An improved means and method is provided for form- lng isolated device regions suitable for the construction of control circuits and devices, in the presence of and isolated from other device regions suitable for the construction of bottom-contact power devices. In a preferred embodiment the desired structure is obtained by growing a first epitaxial layer (11) on a semiconductor substrate (10), providing a patterned mask (12) in which areas (11b) of the epitaxial layer (11) are exposed to be etched, etching recesses (13) In the exposed areas (11b) to a first depth (13a) to leave pedestals (11d) beneath the masked areas (11a), and forming a second (14) and third (15) epitaxial layer on the substrate (11) to fill the recesses (13). The second epitaxial layer (14) is U-shaped and conformally coats the bottom and sides of the recesses (13). The U-shaped layer (14) acts as the isolation layer separating the first epitaxial layer portions in the pedestals (11d) wherein the power devices will be built, from the third epitaxial layer regions (15b, 25b) which fill in the U, where the control devices will be built. The doping of the power device region, isolation layer, and control circuitry region may be optimized separately.

    8.
    发明专利
    未知

    公开(公告)号：DE69232199D1

    公开(公告)日：2001-12-20

    申请号：DE69232199

    申请日：1992-09-14

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

    IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06

    Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

    Semiconductor device having improved frequency response
    9.
    发明专利
    Semiconductor device having improved frequency response 未知

    公开(公告)号：SG44601A1

    公开(公告)日：1997-12-19

    申请号：SG1996003547

    申请日：1992-09-14

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

    IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L27/06

    Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

    10.
    发明专利
    未知

    公开(公告)号：DE69232199T2

    公开(公告)日：2002-06-06

    申请号：DE69232199

    申请日：1992-09-14

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

    IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06

    Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

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