公开(公告)号：JPH10223650A

公开(公告)日：1998-08-21

申请号：JP3407598

申请日：1998-01-30

Applicant: MOTOROLA INC

Inventor： SANDERS PAUL W ,  MACKIE TROY E ,  COSTA JULIO C ,  FREEMAN JR JOHN L ,  WOOD ALAN D

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To enable use for RF power application, by providing a method for coping with the change of resistance value relative to the contact of a bipolar semiconductor device. SOLUTION: A semiconductor device 10 is formed on a semiconductor substrate 11 functioning as a collector region. A base region 12 is formed on the semiconductor substrate 11. An emitter region 52 is formed to be in contact with at least a part of the base region 12. A conducting layer 28 is used so as to make electric connection with the emitter region 52. In order to cope with the problem of a critical oxide layer 27 existing between the emitter region 52 and the conducting layer 28, opposite doping is applied to a part of the conducting layer 28 on the emitter region 52.

公开(公告)号：DE69120305T2

公开(公告)日：1997-01-30

申请号：DE69120305

申请日：1991-01-28

Applicant: MOTOROLA INC

Inventor： JOHNSEN ROBERT J ,  SANDERS PAUL W

IPC: H01L21/336 ,  H01L21/74 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/772 ,  H01L29/08

Abstract: A MOSFET (90,105,170) having a back-side source contact (94,169) and top-side gate (104,166) and drain contacts (98,168) is provided by a structure comprising superposed N (97,136), N- (96,132),P- (95,128), N (92,120) regions arranged between top (99,137) and bottom (93,121) surfaces of the semiconductor die (90,105,170). In a preferred implementation, two trenches (100,108) (148,149) are etched from the top surface (99,137) to the P- (95,128), N (92,120) interface. A buried P- (95,128), N (92,120) short (110,162) is provided in one trench (108,148) and a gate dielectric (102,160) and gate electrode (104,166) are provided over the sidewall P- (95,128) region exposed in the other trench (100,149). This creates a vertical MOSFET (170) in which the N substrate (92,120) forms the source region shorted to the P- body region (95,128) in which the channel (106) is created by the gate (104,166). Superior performance is obtained in RF grounded-source circuit applications.

公开(公告)号：DE19752052A1

公开(公告)日：1998-08-06

申请号：DE19752052

申请日：1997-11-25

Applicant: MOTOROLA INC

Inventor： SANDERS PAUL W ,  FREEMAN JOHN L ,  MACKIE TROY E ,  WOOD ALAN D ,  COSTA JULIO C

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732

公开(公告)号：DE4115128A1

公开(公告)日：1991-11-28

申请号：DE4115128

申请日：1991-05-08

Applicant: MOTOROLA INC

Inventor： SANDERS PAUL W ,  POLLOCK RANDY

IPC: H01L23/12 ,  H01L23/433 ,  H01L23/495 ,  H01L23/50 ,  H01L23/66 ,  H05K1/02 ,  H05K3/34

Abstract: A high frequency, low cost power semiconductor device (60) is provided by combining a semiconductor die (46) with a leadframe (10,12) having a coplanar upper surface (36) with thin external leads (18,20) and a thicker central die bond region (24) whose upper face (16) and sides (42) are covered by an encapsulation (52) but whose lower face (54) is exposed. The leadframe (10,12) desirably has an "H" pattern with the arms (18,20) extending laterally from opposed sides of the encapsulation (52) and down-formed to have their lower surfaces (62) coplanar with the exposed lower face (54) of the central die bond region (16,24) which forms the cross-bar of the "H". The leadframe is monolithic and preferably formed by skiving. The device is especially suited for surface-mounting.

公开(公告)号：DE4115128C2

公开(公告)日：1999-09-30

申请号：DE4115128

申请日：1991-05-08

Applicant: MOTOROLA INC

Inventor： SANDERS PAUL W ,  POLLOCK RANDY

IPC: H01L23/12 ,  H01L23/433 ,  H01L23/495 ,  H01L23/50 ,  H01L23/66 ,  H05K1/02 ,  H05K3/34 ,  H01L21/60 ,  H01L23/31

Abstract: A high frequency, low cost power semiconductor device (60) is provided by combining a semiconductor die (46) with a leadframe (10,12) having a coplanar upper surface (36) with thin external leads (18,20) and a thicker central die bond region (24) whose upper face (16) and sides (42) are covered by an encapsulation (52) but whose lower face (54) is exposed. The leadframe (10,12) desirably has an "H" pattern with the arms (18,20) extending laterally from opposed sides of the encapsulation (52) and down-formed to have their lower surfaces (62) coplanar with the exposed lower face (54) of the central die bond region (16,24) which forms the cross-bar of the "H". The leadframe is monolithic and preferably formed by skiving. The device is especially suited for surface-mounting.

公开(公告)号：DE69232199D1

公开(公告)日：2001-12-20

申请号：DE69232199

申请日：1992-09-14

Applicant: MOTOROLA INC

Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06

Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

公开(公告)号：SG44601A1

公开(公告)日：1997-12-19

申请号：SG1996003547

申请日：1992-09-14

Applicant: MOTOROLA INC

Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L27/06

Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

公开(公告)号：DE69120305D1

公开(公告)日：1996-07-25

申请号：DE69120305

申请日：1991-01-28

Applicant: MOTOROLA INC

Inventor： JOHNSEN ROBERT J ,  SANDERS PAUL W

IPC: H01L21/336 ,  H01L21/74 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/772 ,  H01L29/08

Abstract: A MOSFET (90,105,170) having a back-side source contact (94,169) and top-side gate (104,166) and drain contacts (98,168) is provided by a structure comprising superposed N (97,136), N- (96,132),P- (95,128), N (92,120) regions arranged between top (99,137) and bottom (93,121) surfaces of the semiconductor die (90,105,170). In a preferred implementation, two trenches (100,108) (148,149) are etched from the top surface (99,137) to the P- (95,128), N (92,120) interface. A buried P- (95,128), N (92,120) short (110,162) is provided in one trench (108,148) and a gate dielectric (102,160) and gate electrode (104,166) are provided over the sidewall P- (95,128) region exposed in the other trench (100,149). This creates a vertical MOSFET (170) in which the N substrate (92,120) forms the source region shorted to the P- body region (95,128) in which the channel (106) is created by the gate (104,166). Superior performance is obtained in RF grounded-source circuit applications.

公开(公告)号：DE69232199T2

公开(公告)日：2002-06-06

申请号：DE69232199

申请日：1992-09-14

Applicant: MOTOROLA INC

Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06

Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

公开(公告)号：SG43147A1

公开(公告)日：1997-10-17

申请号：SG1996004446

申请日：1991-01-28

Applicant: MOTOROLA INC

Inventor： JOHNSE ROBERT J ,  SANDERS PAUL W

IPC: H01L21/336 ,  H01L21/74 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/772

Abstract: A MOSFET (90,105,170) having a back-side source contact (94,169) and top-side gate (104,166) and drain contacts (98,168) is provided by a structure comprising superposed N (97,136), N- (96,132),P- (95,128), N (92,120) regions arranged between top (99,137) and bottom (93,121) surfaces of the semiconductor die (90,105,170). In a preferred implementation, two trenches (100,108) (148,149) are etched from the top surface (99,137) to the P- (95,128), N (92,120) interface. A buried P- (95,128), N (92,120) short (110,162) is provided in one trench (108,148) and a gate dielectric (102,160) and gate electrode (104,166) are provided over the sidewall P- (95,128) region exposed in the other trench (100,149). This creates a vertical MOSFET (170) in which the N substrate (92,120) forms the source region shorted to the P- body region (95,128) in which the channel (106) is created by the gate (104,166). Superior performance is obtained in RF grounded-source circuit applications.