公开(公告)号：HK1004585A1

公开(公告)日：1998-11-27

申请号：HK98102902

申请日：1998-04-07

Applicant: MOTOROLA INC

Inventor： DABBISH EZZAT A ,  BYRNS JOHN P ,  MCCLAUGHRY MICHAEL J ,  PUHL LARRY C ,  BROWN DANIEL P ,  ZIOLKO ERIC F ,  BRIGHT MICHAEL W

IPC: H04L9/10 ,  G06F21/00 ,  H04K1/00 ,  H04L9/06 ,  H04L9/14 ,  H04K

Abstract: A cryptographic apparatus for encrypting and decrypting digital words includes a mechanism that permits a cipher algorithm to be electronically stored after the manufacture of the apparatus. The storing mechanism includes at least one electrically erasable, programmable gate array containing a portion of the cipher algorithm and at least one random access memory device coupled to the array for storing digital data generated by the algorithm. A mechanism which is coupled to the gate array and memory device controls the execution of the algorithm for each digital word thereby decrypting encrypted digital words and encrypting non-encrypted digital words.

公开(公告)号：AT139392T

公开(公告)日：1996-06-15

申请号：AT89901906

申请日：1989-01-03

Applicant: MOTOROLA INC

Inventor： DABBISH EZZAT A ,  BYRNS JOHN P ,  MCCLAUGHRY MICHAEL J ,  PUHL LARRY C ,  BROWN DANIEL P ,  ZIOLKO ERIC F ,  BRIGHT MICHAEL W

IPC: H04L9/10 ,  G06F21/00 ,  H04K1/00 ,  H04L9/06 ,  H04L9/14

Abstract: A cryptographic apparatus for encrypting and decrypting digital words includes a mechanism that permits a cipher algorithm to be electronically stored after the manufacture of the apparatus. The storing mechanism includes at least one electrically erasable, programmable gate array containing a portion of the cipher algorithm and at least one random access memory device coupled to the array for storing digital data generated by the algorithm. A mechanism which is coupled to the gate array and memory device controls the execution of the algorithm for each digital word thereby decrypting encrypted digital words and encrypting non-encrypted digital words.

公开(公告)号：CA1336721C

公开(公告)日：1995-08-15

申请号：CA585307

申请日：1988-12-08

Applicant: MOTOROLA INC

Inventor： DABBISH EZZAT A ,  BYRNS JOHN P ,  MCCLAUGHRY MICHAEL J ,  PUHL LARRY C ,  BROWN DANIEL P ,  ZIOLKO ERIC F ,  BRIGHT MICHAEL W

IPC: H04L9/10 ,  G06F21/00 ,  H04K1/00 ,  H04L9/06 ,  H04L9/14 ,  H04L9/18

Abstract: A cryptographic apparatus for encrypting and decrypting digital words includes a mechanism that permits a cipher algorithm to be electronically stored after the manufacture of the apparatus. The storing mechanism includes at least one electrically erasable, programmable gate array containing a portion of the cipher algorithm and at least one random access memory device coupled to the array for storing digital data generated by the algorithm. A mechanism which is coupled to the gate array and memory device controls the execution of the algorithm for each digital word thereby decrypting encrypted digital words and encrypting non-encrypted digital words.

公开(公告)号：DE2437152A1

公开(公告)日：1975-02-20

申请号：DE2437152

申请日：1974-08-01

Applicant: MOTOROLA INC

Inventor： BRAUN WILLIAM V ,  ZIOLKO ERIC F ,  BYRNS JOHN P

IPC: H04J3/00 ,  H04B1/66 ,  H04J3/18 ,  H04Q11/04

Abstract: A multiplex data transmission circuit is used to carry n signals at a first recurrence rate in a limited bandwidth each compressed in time, from which are derived a series of signal segments of specific time duration at a recurrence rate n times greater. The bandwidth for each signal segment is limited to a second band with lower limiting frequency n times the upper limit of the first bandwidth and upper limit n times the upper limit of the first, the second train of signal segments being that sent to line. This ensures optimum usage of the available bandwidth and the same signal/noise ratio in all channels when using FN transmission.

公开(公告)号：CA1172331A

公开(公告)日：1984-08-07

申请号：CA384151

申请日：1981-08-19

Applicant: MOTOROLA INC

Inventor： BYRNS JOHN P

IPC: H03M5/06 ,  G06F20060101 ,  G06F11/30 ,  G06F13/38 ,  H04B14/00 ,  H04L1/02 ,  H04L5/14 ,  H04L25/02 ,  H04L25/49 ,  H04Q20060101 ,  H04Q1/30 ,  H04Q3/58 ,  H04L11/02 ,  H03K5/156

Abstract: A data transmission system is described where data signals are bidirectionally transmitted between a data transmitter and a plurality of data receivers in a selfclocking bit streams carried on true data and complement data signal lines and a non-return-to-zero (NRZ) bit streams on a return data signal line. According to an inventive data transmission scheme, data signals are transmitted by the data transmitter by utilizing the four possible two-bit binary states of the true data and complement data signal lines. Of the four two-bit binary states, a word state is provided before and after the data signal and a one state or zero state followed by a bit state is provided for each bit of the data signal. The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal. In response to the bit clock signal, the NRZ data signal is serially shifted into a register while a previously parallel loaded return data signal is shifted out of the register and applied to the return data signal line. The inventive data transmission scheme is self-clocking and highly immune to speed and timing variations in the transmission. The inventive data transmission may be advantageously utilized for data transmission in many different data transmission systems, such as computer systems for data transmission between a microprocessor and peripheral units and control systems for data transmission between a central control station and geographically remote stations.

公开(公告)号：CA1157120A

公开(公告)日：1983-11-15

申请号：CA368037

申请日：1981-01-07

Applicant: MOTOROLA INC

Inventor： MCCLAUGHRY MICHAEL J ,  BYRNS JOHN P

IPC: H04L7/033 ,  H04L25/06 ,  H04L25/49 ,  H04L1/00

Abstract: A demodulator is described for demodulating phaseencoded data signals transmitted on a noisy communication channel, such as, for example, radio communication channels of a radio communication system. The demodulator includes a digital phase-locked loop for phase-locking to the mid-bit transitions of the phase-encoded data signal, which, in the preferred embodiment is encoded according to the well known Manchester coding format, and further includes demodulating circuitry for sampling the phaseencoded data signal a predetermined number of times, weighting the samples according to predetermined weighting factors, totalizing the weighted samples for each bit interval and comparing the totalized samples to a predetermined threshold value for ascertaining the logical state of each bit of the phase-encoded data signal. For example, if the magnitude of the totalized samples is greater than or equal to the threshold value, a logical one state may be provided for the decoded data signal, and, if the magnitude of the totalized samples is less than the threshold value, a logical zero state may be provided for the decoded data signal. In preferred embodiments of the present invention, the weighting factors assigned to each sample may be either binary weighted or sine weighted, although any suitable weighting factors may be utilized depending on the characteristics of the phase-encoded data signal. The phase-encoded data signal demodulator embodying the present invention is particularly well adapted for demodulating high speed, phase-encoded data signals transmitted over radio channels to mobile and portable stations of a radio communication system.