Abstract:
PROBLEM TO BE SOLVED: To provide a forming method of a compound semiconductor element which restrains performance change due to the change of operation temperature. SOLUTION: A semiconductor element 20 is formed on a compound semiconductor substrate 21. Orientation of the semiconductor element 20 on the surface 40 of the compound semiconductor substrate 21 is performed in such a manner that physical forces generated as the result of heating and as the result of cooling become essentially indentical. By the effect of this orientation, the change of a drain-source current of the semiconductor element 20 is restrained in the case that the element 20 is operated at different temperatures.
Abstract:
PROBLEM TO BE SOLVED: To provide a passive part, an ESD part and a logic part with a monolithic integration as a high-frequency power transistor structure with high cost efficiency and reliability. SOLUTION: A high-frequency power FET device 22 forms a monolithic high-frequency integrated circuit structure 10 by integrating the passive parts 23, 24, 26, 28, 31, electric static discharge (ESD) devices 27, 127, 227, and/or a logic structure 29 together on a semiconductor body 13. The high-frequency power FET device 22 includes a source grounding structure. The logic structure 29 uses the high-frequency power FET structure of the source grounding structure as one of the devices of a CMOS constitution. COPYRIGHT: (C)2003,JPO
Abstract:
PROBLEM TO BE SOLVED: To enable use for RF power application, by providing a method for coping with the change of resistance value relative to the contact of a bipolar semiconductor device. SOLUTION: A semiconductor device 10 is formed on a semiconductor substrate 11 functioning as a collector region. A base region 12 is formed on the semiconductor substrate 11. An emitter region 52 is formed to be in contact with at least a part of the base region 12. A conducting layer 28 is used so as to make electric connection with the emitter region 52. In order to cope with the problem of a critical oxide layer 27 existing between the emitter region 52 and the conducting layer 28, opposite doping is applied to a part of the conducting layer 28 on the emitter region 52.
Abstract:
A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.
Abstract:
A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.
Abstract:
A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.