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公开(公告)号：AU2003214195A1
公开(公告)日：2003-11-03
申请号：AU2003214195
申请日：2003-03-17
Applicant: MOTOROLA INC
Inventor： DYAS ROBERT , CASTRO FRANCISCO , HARTON AUSTIN , HEROLD BARRY
Abstract: A pixel image sensor having an array of pixel elements arranged in a color mosaic pattern, each pixel element being responsive to light of a particular color. Each pixel element is supplied with a reference voltage signal corresponding to the color of light to which the pixel element is responsive. The reference voltage signal determined the sensitivity of the pixel element. The white balance of the image sensor is adjusted by varying independently the reference voltage signals for each color. The color mosaic pattern of the array may include a pixel element responsive to white light. The output from the white pixel sensors may be used to adjust the color constancy of the image sensor. The image array reduces the need for post-capture processing of the image for white balancing, by incorporating the white balance operation into the capture process.
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公开(公告)号：DE69030091D1
公开(公告)日：1997-04-10
申请号：DE69030091
申请日：1990-07-09
Applicant: MOTOROLA INC
Inventor： TAHERNIA OMID , DAVIS WALTER , HEROLD BARRY
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公开(公告)号：DE69028113D1
公开(公告)日：1996-09-19
申请号：DE69028113
申请日：1990-05-18
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY , TAHERNIA OMID , DAVIS WALTER , RIVAS MARIO
Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
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公开(公告)号：DE69030091T2
公开(公告)日：1997-09-18
申请号：DE69030091
申请日：1990-07-09
Applicant: MOTOROLA INC
Inventor： TAHERNIA OMID , DAVIS WALTER , HEROLD BARRY
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公开(公告)号：DE69026259D1
公开(公告)日：1996-05-02
申请号：DE69026259
申请日：1990-06-21
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY , TAHERNIA OMID
Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.
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Patent Agency Ranking
公开(公告)号：AU2002366514A1
公开(公告)日：2003-06-23
申请号：AU2002366514
申请日：2002-11-22
Applicant: MOTOROLA INC
Inventor： CASTRO FRANCISCO , HEROLD BARRY , HARTON AUSTIN
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公开(公告)号：DE69028113T2
公开(公告)日：1997-03-06
申请号：DE69028113
申请日：1990-05-18
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY , TAHERNIA OMID , DAVIS WALTER , RIVAS MARIO
Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
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公开(公告)号：DE69026259T2
公开(公告)日：1996-10-02
申请号：DE69026259
申请日：1990-06-21
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY , TAHERNIA OMID
Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.
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公开(公告)号：DE3486195T2
公开(公告)日：1993-12-16
申请号：DE3486195
申请日：1984-10-30
Applicant: MOTOROLA INC
Inventor： DAVIS WALTER , HEROLD BARRY , LITTLE WENDELL
IPC: G06F1/00 , G06F1/04 , G06F1/08 , G06F1/32 , G06F15/78 , H03L7/089 , H03L7/107 , H03L7/183 , G06F7/68
Abstract: A microcomputer (104) having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer (200) which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer (200) is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the execution requirements change, the synthesizer (200) responds to provide only the frequency required. Thus, the power dissipated by the entire microcomputer system is minimized.
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公开(公告)号：DE3486195D1
公开(公告)日：1993-09-09
申请号：DE3486195
申请日：1984-10-30
Applicant: MOTOROLA INC
Inventor： DAVIS WALTER , HEROLD BARRY , LITTLE WENDELL
IPC: G06F1/00 , G06F1/04 , G06F1/08 , G06F1/32 , G06F15/78 , H03L7/089 , H03L7/107 , H03L7/183 , G06F7/68
Abstract: A microcomputer (104) having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer (200) which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer (200) is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the execution requirements change, the synthesizer (200) responds to provide only the frequency required. Thus, the power dissipated by the entire microcomputer system is minimized.
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