公开(公告)号：DE69028113T2

公开(公告)日：1997-03-06

申请号：DE69028113

申请日：1990-05-18

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY ,  TAHERNIA OMID ,  DAVIS WALTER ,  RIVAS MARIO

IPC: H03J5/02 ,  H03L7/18 ,  H03J1/00

Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

公开(公告)号：DE69028113D1

公开(公告)日：1996-09-19

申请号：DE69028113

申请日：1990-05-18

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY ,  TAHERNIA OMID ,  DAVIS WALTER ,  RIVAS MARIO

IPC: H03J5/02 ,  H03L7/18 ,  H03J1/00

Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.