公开(公告)号：AU5317200A

公开(公告)日：2001-05-10

申请号：AU5317200

申请日：2000-06-02

Applicant: MOTOROLA INC

Inventor： TALIN ALBERT ALEC ,  COLL BERNARD F ,  DEAN KENNETH A ,  JASKIE JAMES E ,  HOWARD EMMETT

IPC: H01J9/02

Abstract: A method for fabricating an electron-emissive film (100) includes the steps of providing a powder (124), which has a plurality of carbon nanotubes (104); providing a substrate (102), a surface (103) of which defines a plurality of interstices (107); and dry spraying powder (124) onto surface (103) of substrate (102). The adjustable parameters of the dry spraying step include a separation distance of a spray nozzle (120) from surface (103), a spray angle between a spray (121) and surface (103), and a nozzle pressure at an opening (123) of spray nozzle (120).The separation distance, spray angle, and nozzle pressure are selected to achieve, for example, uniformity of electron-emissive film (100) and adhesion of carbon nanotubes (104) to substrate (102). They can also be selected to achieve a perpendicular orientation of a length-wise axis (105) of each of carbon nanotubes (104) with respect to surface (103) and to achieve the break down of aggregates of carbon nanotubes (104), so that carbon nanotubes (104) are deposited on substrate (102) substantially as individually isolated carbon nanotubes (104).

公开(公告)号：WO2009017929A3

公开(公告)日：2009-04-09

申请号：PCT/US2008069004

申请日：2008-07-02

Applicant: MOTOROLA INC ,  YOUNG STEVEN ,  DAUKSHER WILLIAM ,  HOWARD EMMETT ,  WESTON DONALD

Inventor： YOUNG STEVEN ,  DAUKSHER WILLIAM ,  HOWARD EMMETT ,  WESTON DONALD

IPC: H01L21/331

CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J2201/3195

Abstract: A method for minimizing fabrication defects in ballast contact to a conductor in monolithically integrated semiconductor devices includes forming a sloping sidewall (318, 424) in both an insulating layer (106, 718) overlying a conductive layer (104, 714) by etching with a an RF biased fluorine based chemistry and an RF biased chlorine based chemistry, respectively, as defined by a single resist layer (108) having a sloped sidewall (212). A ballast layer (526, 726) is deposited on the structure (100, 700) and metal contacts (632, 634, 636, 638, 722) are disposed on the ballast layer (526, 722).

Abstract translation: 一种用于使单片集成半导体器件中的导体的镇流器接触中的制造缺陷最小化的方法包括：通过用导电层（104,714）蚀刻的绝缘层（106,718）中的两者来形成倾斜侧壁（318,424） 分别由具有倾斜侧壁（212）的单个抗蚀剂层（108）限定的RF偏压氟基化学物质和RF偏压氯基化学物质。 在结构（100,700）上沉积压载层（526,726），并且在压载层（526,722）上设置金属接触件（632,634,636,638,722）。