公开(公告)号：WO2006130333B1

公开(公告)日：2008-06-26

申请号：PCT/US2006018713

申请日：2006-05-12

Applicant: MOTOROLA INC ,  GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

Inventor： GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

IPC: H03L7/06

CPC classification number: H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1976

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract translation: 公开了一种用于减少锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括适应模式电荷泵（204），正常模式电荷泵（206）以及应用于这些电荷泵的受控细流电流（208），（210）的使用以最小化PLL（100）的瞬态响应， 。

公开(公告)号：EP0563125A4

公开(公告)日：1997-02-26

申请号：EP92901158

申请日：1991-11-15

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J

IPC: H04B1/04 ,  H03F1/02 ,  H03F3/72 ,  H03G3/30 ,  H04B1/16 ,  H04W28/04 ,  H04W88/00

CPC classification number: H03G3/3047 ,  H03F1/02 ,  H03F1/0261 ,  H03F3/24 ,  H03F3/72 ,  H03G3/3042 ,  H04B1/1615 ,  H04B2001/045 ,  H04W88/00

Abstract: An amplifier (102) which can be dynamically biased is disclosed. A controller (118) determines when to change the bias to the amplifier (102), in order to achieve low frequency splatter. This is accomplished by changing the bias level of amplifier (102) between a substantially linear (class A) mode of operation, and a substantially nonlinear (class B) mode of operation. During the critical periods when the amplifier (102) is being turned into and out of operation, the amplifier (102) is placed in a substantially linear mode of operation, thereby reducing the output harmonics which develop. In another aspect of the invention a radio (300) which employs a dynamically biased amplifier (102) is disclosed.

公开(公告)号：WO2006130333A3

公开(公告)日：2008-05-08

申请号：PCT/US2006018713

申请日：2006-05-12

Applicant: MOTOROLA INC ,  GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

Inventor： GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

IPC: H03L7/06

CPC classification number: H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1976

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract translation: 公开了一种用于减小锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括适应模式电荷泵（204），正常模式电荷泵（206）以及施加到这些电荷泵的受控涓流（208），（210）的使用以最小化PLL（100）的瞬态响应， 。

公开(公告)号：AU3707093A

公开(公告)日：1994-04-21

申请号：AU3707093

申请日：1993-04-22

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J

IPC: H04B1/04 ,  H03F1/02 ,  H03F3/72 ,  H03G3/30 ,  H04B1/16 ,  H04W28/04 ,  H04W88/00 ,  H03F3/19 ,  H03F3/21 ,  H03F3/24 ,  H03F1/06 ,  H04B1/40 ,  H04B7/26 ,  H03G1/04

Abstract: An amplifier (102) which can be dynamically biased is disclosed. A controller (118) determines when to change the bias to the amplifier (102), in order to achieve low frequency splatter. This is accomplished by changing the bias level of amplifier (102) between a substantially linear (class A) mode of operation, and a substantially nonlinear (class B) mode of operation. During the critical periods when the amplifier (102) is being turned into and out of operation, the amplifier (102) is placed in a substantially linear mode of operation, thereby reducing the output harmonics which develop. In another aspect of the invention a radio 300 which employs a dynamically biased amplifier (102) is disclosed.

公开(公告)号：FI932757A

公开(公告)日：1993-06-16

申请号：FI932757

申请日：1993-06-16

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J

IPC: H04B1/04 ,  H03F1/02 ,  H03F3/72 ,  H03G3/30 ,  H04B1/16 ,  H04W28/04 ,  H04W88/00

Abstract: An amplifier (102) which can be dynamically biased is disclosed. A controller (118) determines when to change the bias to the amplifier (102), in order to achieve low frequency splatter. This is accomplished by changing the bias level of amplifier (102) between a substantially linear (class A) mode of operation, and a substantially nonlinear (class B) mode of operation. During the critical periods when the amplifier (102) is being turned into and out of operation, the amplifier (102) is placed in a substantially linear mode of operation, thereby reducing the output harmonics which develop. In another aspect of the invention a radio 300 which employs a dynamically biased amplifier (102) is disclosed.

公开(公告)号：CA2670521C

公开(公告)日：2013-02-12

申请号：CA2670521

申请日：2007-09-18

Applicant: MOTOROLA INC

Inventor： GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

IPC: H03L7/06 ,  H03L7/10

Abstract: A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).

公开(公告)号：AU2007325558A1

公开(公告)日：2008-06-05

申请号：AU2007325558

申请日：2007-09-18

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J ,  DUBOV VADIM ,  GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A

IPC: H03L7/06

Abstract: A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).

公开(公告)号：MX9102462A

公开(公告)日：1992-06-01

申请号：MX9102462

申请日：1991-12-10

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J

IPC: H04B1/04 ,  H03F1/02 ,  H03F3/72 ,  H03G3/30 ,  H04B1/16 ,  H04W28/04 ,  H04W88/00 ,  H03L7/00

Abstract: An amplifier (102) which can be dynamically biased is disclosed. A controller (118) determines when to change the bias to the amplifier (102), in order to achieve low frequency splatter. This is accomplished by changing the bias level of amplifier (102) between a substantially linear (class A) mode of operation, and a substantially nonlinear (class B) mode of operation. During the critical periods when the amplifier (102) is being turned into and out of operation, the amplifier (102) is placed in a substantially linear mode of operation, thereby reducing the output harmonics which develop. In another aspect of the invention a radio 300 which employs a dynamically biased amplifier (102) is disclosed.

公开(公告)号：ES2280901T3

公开(公告)日：2007-09-16

申请号：ES04100346

申请日：1999-10-14

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J ,  TURNEY WILLIAM J ,  GAILUS PAUL H ,  CLARK EDWARD T ,  DOREVITCH JOSHUA E ,  MANSFIELD TERRY K

IPC: H04B1/28 ,  H04B1/00

Abstract: Un subsistema receptor de radiofrecuencia, RF, sigma-delta integrado (200) que comprende: un convertidor analógico-digital sigma-delta multi-modo (215) para proporcionar una salida sencilla y multi-bit; un mezclador digital (221) para la creación de señales banda base digitales en fase (I) y en fase de cuadratura (Q); una red de decimación programable (221) para reducir la frecuencia de las señales banda base digitales en fase y en cuadratura; y una red de formateo programable (223) para organizar las componentes en fase y en cuadratura de la red de decimación (221) para el procesamiento de señal posterior, caracterizado porque dicha red de formateo programable (223) comprende un medio para producir una primera palabra de 16 bits de la señal en fase, y una segunda palabra de 16 bits de la señal en cuadratura y una tercera palabra de 16 bits para su uso como una información de control automático de ganancia, comprendiendo dicha red de formateo programable (223) además una interfaz serie síncrona para insertar información síncrona para determinar las porciones de comienzo y parada para cada una de dichas palabras para su uso posterior en el procesamiento de la señal.

公开(公告)号：DE69935173D1

公开(公告)日：2007-03-29

申请号：DE69935173

申请日：1999-10-14

Applicant: MOTOROLA INC

Inventor： MARTIN WILLIAM J ,  TURNEY WILLIAM J ,  GAILUS PAUL H ,  CLARK EDWARD T ,  DOREVITCH JOSHUA E ,  MANSFIELD TERRY K

IPC: H04B1/28 ,  H04B1/00

Abstract: An integrated sigma-delta radio frequency (RF) receiver subsystem (200) and method utilizes a multi-mode sigma-delta analog-to-digital converter (215) for providing a single and multi-bit output. A programmable decimation network (221) for reducing the frequency of the in-phase and quadrature bit stream and a programmable formatting network (223) are also used for organizing the in-phase and quadrature components from the decimation network (221) for subsequent signal processing. The invention offers a highly integrated digital/analog RF receiver back-end which incorporates integrated filtering and a smart gain control that is compatible for use with other receiver systems and offering superior performance characteristics.