公开(公告)号：WO2003013071A1

公开(公告)日：2003-02-13

申请号：PCT/US2002/022178

申请日：2002-07-13

Applicant: MOTOROLA, INC.

Inventor： MANSOURI, Mack ,  STEWART, Daniel ,  ROSSI, Steven

IPC: H04L12/54

CPC classification number: H04N21/226 ,  H04N21/236

Abstract: A format programmable hardware packetizer (110) receives real-time raw input data (125) from a multimedia data source (103) via an analog to digital converter (105) and a data encoder (120) gated by encoder interrupts (127). The real-time raw input data is buffered in an internal byte collector of the packetizer (110). A main CPU interrupt (117) is issued to the main processor (130) when a packet boundary code is received. The packetizer (110) formats the data according to a desired format selected on line (115) for dump to the main memory (140) while providing a managed, much lower level of interrupts to the main processor (130) on the CPU interrupt line (117). A plurality of hardware packetizers (110) can be deployed according to alternative constructions for efficient real time packetizing in various selected formats.

Abstract translation: 格式可编程硬件分组器（110）经由模数转换器（105）和由编码器中断（127）门控的数据编码器（120）从多媒体数据源（103）接收实时原始输入数据（125）。 实时原始输入数据被缓存在打包器（110）的内部字节收集器中。 当接收到分组边界码时，主CPU中断（117）被发送到主处理器（130）。 打包器（110）根据在线（115）上选择的期望格式将数据格式化，以转储到主存储器（140），同时向CPU中断线上的主处理器（130）提供被管理的，低得多的中断级别 （117）。 可以根据替代结构部署多个硬件打包器（110），以便以各种选择的格式进行有效的实时打包。

公开(公告)号：EP0920733A1

公开(公告)日：1999-06-09

申请号：EP97906615.0

申请日：1997-02-13

Applicant: MOTOROLA, INC.

Inventor： MANSOURI, Mack ,  BONTRAGER, Richard

IPC: H04B7 ,  H04B1

CPC classification number: H04B7/005 ,  H04B1/1027

Abstract: An apparatus for use in a receiver (100) of a wireless communication system is provided. The apparatus comprises a first filter (340) having a first cutoff frequency, a second filter (350) having a second cutoff frequency, a first data bit estimator (360) coupled to the first filter (340), a second data bit estimator (361) coupled to the second filter (350), a third data bit estimator (363), and decision logic (370) dynamically selecting one of the first and second filters based on a first bit count from the first data bit estimator (360), a second bit count from the second data bit estimator (361), and a third bit count from the third data bit estimator (363).

公开(公告)号：WO1998015056A1

公开(公告)日：1998-04-09

申请号：PCT/US1997011435

申请日：1997-07-08

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  KUNDMANN, Thomas ,  MANSOURI, Mack ,  TARRAB, Moshe ,  PISEK, Eran

IPC: H03H07/30

CPC classification number: H04L25/03178 ,  G06F7/5443

Abstract: A filter co-processor (103, 109 and 109 fig.) within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signals (112) are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values for demodulation, the filter co-processor is able to process information in a given amount of time, leading to increased processing when compared to the prior art.

Abstract translation: 数字信号处理器（DSP）内的滤波器协处理器（103,109和109图）利用均衡过程中调制信号的正交特性。 由于在接收之后，仅接收信号（112）的某些实数/虚数值对于解调是有用的，所以滤波器协处理器仅处理这些值以估计所发送的信号。 通过仅处理那些用于解调的值，滤波器协处理器能够在给定的时间量内处理信息，导致与现有技术相比增加的处理。

公开(公告)号：WO1997042721A1

公开(公告)日：1997-11-13

申请号：PCT/US1997002368

申请日：1997-02-13

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  MANSOURI, Mack ,  BONTRAGER, Richard

IPC: H04B01/10

CPC classification number: H04B7/005 ,  H04B1/1027

Abstract: An apparatus for use in a receiver (100) of a wireless communication system is provided. The apparatus comprises a first filter (340) having a first cutoff frequency, a second filter (350) having a second cutoff frequency, a first data bit estimator (360) coupled to the first filter (340), a second data bit estimator (361) coupled to the second filter (350), a third data bit estimator (363), and decision logic (370) dynamically selecting one of the first and second filters based on a first bit count from the first data bit estimator (360), a second bit count from the second data bit estimator (361), and a third bit count from the third data bit estimator (363).

Abstract translation: 提供一种在无线通信系统的接收机（100）中使用的装置。 该装置包括具有第一截止频率的第一滤波器（340），具有第二截止频率的第二滤波器（350），耦合到第一滤波器（340）的第一数据比特估计器（360），第二数据比特估计器 361），第三数据比特估计器（363）和决定逻辑（370），基于来自第一数据比特估计器（360）的第一比特计数动态地选择第一和第二滤波器之一， ，来自第二数据比特估计器（361）的第二比特计数，以及来自第三数据比特估计器（363）的第三比特计数。