公开(公告)号：DE60115437D1

公开(公告)日：2006-01-05

申请号：DE60115437

申请日：2001-06-20

Applicant: NANONEXUS INC

Inventor： MOK SAMMY ,  CHONG CHIUNG

IPC: G01R31/26 ,  G01R1/067 ,  G01R1/073 ,  H01L21/66 ,  H01L23/12 ,  H01L23/31 ,  H01L23/32 ,  H01L23/48 ,  H01L23/485

Abstract: Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.

公开(公告)号：AU2003272205A8

公开(公告)日：2004-01-06

申请号：AU2003272205

申请日：2003-06-23

Applicant: NANONEXUS INC

Inventor： CHONG FU-CHIUNG ,  LAHIRI SYAMAL KUMAR ,  MOK SAMMY ,  SWIATOWIEC FRANK ,  HAEMER JOSEPH MICHAEL

IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H05K3/40 ,  H05K7/10 ,  G01R31/02

Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.

公开(公告)号：AU2003272205A1

公开(公告)日：2004-01-06

申请号：AU2003272205

申请日：2003-06-23

Applicant: NANONEXUS INC

Inventor： MOK SAMMY ,  CHONG FU-CHIUNG ,  SWIATOWIEC FRANK ,  LAHIRI SYAMAL KUMAR ,  HAEMER JOSEPH MICHAEL

IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H05K3/40 ,  H05K7/10

Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.

公开(公告)号：AU5171800A

公开(公告)日：2000-12-18

申请号：AU5171800

申请日：2000-05-26

Applicant: NANONEXUS INC

Inventor： CHONG FU CHIUNG ,  MOK SAMMY

IPC: G01R31/26 ,  G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  G11C29/56 ,  H01L21/66 ,  G06F11/00

公开(公告)号：AU2003259105A8

公开(公告)日：2004-02-02

申请号：AU2003259105

申请日：2003-07-10

Applicant: NANONEXUS INC

Inventor： CHONG FU-CHIUNG ,  FELDMAN IRA ,  MOK SAMMY

IPC: G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  G01R31/02

Abstract: The invention provides a mosaic decal probe, in which a mosaic of probe chips is assembled into a thin membrane that is suspended in a ring which is made of a material that has a TCE matching that of silicon. The membrane is mounted on the ring in tension, such as it stays in tension throughout a functional temperature range. In this way, the membrane exhibits a functional TCE matching that of the ring. The probe chip preferably has spring contacts on both sides. Apertures are cut in the membrane to allow the spring contacts on one side of the membrane to protrude through the membrane and contact the printed wiring board. The spring contacts which contact the printed wiring board are allowed to slide during temperature excursions, thereby decoupling the TCE mismatch between the probe chip and the printed wiring board. Two preferred embodiments are currently contemplated. A first embodiment of the invention uses a low-count mosaic comprised of few probe chips, for example four probe chips. The probe chips have the same TCE as the wafer under test, e.g. silicon. In this embodiment, the probe chip is peripherally attached to the membrane. A second embodiment of the invention provides a high-count mosaic, using a high number of probe chips, for example nine or more probe chips. In this embodiment, the probe chips are smaller and can have a slight TCE difference from that of the test wafer, e.g. silicon. For example, the probe chips may be made out of a ceramic material. This embodiment of the invention uses a center attachment to secure the probe chips to the membrane.

公开(公告)号：AU2003218288A1

公开(公告)日：2003-10-08

申请号：AU2003218288

申请日：2003-03-18

Applicant: NANONEXUS INC

Inventor： SWIATOWIEC FRANK ,  CHONG FU-CHIUNG ,  MOK SAMMY ,  CHIEH ERH-KONG ,  MILTER ROMAN L ,  HAEMER JOSEPH M ,  LIN CHANG-MING ,  CHEN YI-HSENG ,  DOAN DAVID THANH ,  LAHIRI SYAMAL KUMAR

IPC: B81B3/00 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H01L23/48 ,  H01R13/24 ,  H05K3/40 ,  H05K7/10 ,  H01R12/04 ,  H01R12/36

Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs (507), which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs (507). In addition, the invention also presents a method to fabricate the springs (507) that allow passage of relatively higher current without significantly degrading their lifetime.

公开(公告)号：AU6863001A

公开(公告)日：2002-01-02

申请号：AU6863001

申请日：2001-06-20

Applicant: NANONEXUS INC

Inventor： MOK SAMMY ,  CHONG FU CHIUNG

IPC: G01R31/26 ,  G01R1/067 ,  G01R1/073 ,  H01L21/66 ,  H01L23/12 ,  H01L23/31 ,  H01L23/32 ,  H01L23/48 ,  H01L23/485

Abstract: Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.

公开(公告)号：DE60115437T2

公开(公告)日：2006-07-27

申请号：DE60115437

申请日：2001-06-20

Applicant: NANONEXUS INC

Inventor： MOK SAMMY ,  CHONG CHIUNG

IPC: G01R1/073 ,  G01R31/26 ,  G01R1/067 ,  H01L21/66 ,  H01L23/12 ,  H01L23/31 ,  H01L23/32 ,  H01L23/48 ,  H01L23/485

Abstract: Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.

公开(公告)号：AU6509500A

公开(公告)日：2001-02-19

申请号：AU6509500

申请日：2000-07-28

Applicant: NANONEXUS INC

Inventor： MOK SAMMY ,  CHONG FU CHIUNG

IPC: G01R31/26 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/66

公开(公告)号：AU5156300A

公开(公告)日：2000-12-18

申请号：AU5156300

申请日：2000-05-23

Applicant: NANONEXUS INC

Inventor： MOK SAMMY ,  CHONG FU CHIUNG

IPC: G01R31/26 ,  G01R1/06 ,  G01R1/073 ,  H01L21/66

Abstract: Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Interleaved spring probe tip designs are defined which allow multiple probe contacts on very small integrated circuit pads. The shapes of probe tips are preferably defined to control the depth of probe tip penetration between a probe spring and a pad or trace on an integrated circuit device. Improved protective coating techniques for spring probes are also disclosed, offering increased reliability and extended useful service lives for probe card assemblies.