中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.022 seconds)

    Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs
    3.
    发明专利
    Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs 未知

    公开(公告)号：AU2003272205A8

    公开(公告)日：2004-01-06

    申请号：AU2003272205

    申请日：2003-06-23

    Applicant: NANONEXUS INC

    Inventor： CHONG FU-CHIUNG ,  LAHIRI SYAMAL KUMAR ,  MOK SAMMY ,  SWIATOWIEC FRANK ,  HAEMER JOSEPH MICHAEL

    IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H05K3/40 ,  H05K7/10 ,  G01R31/02

    Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.

    CONSTRUCTION STRUCTURES AND MANUFACTURING PROCESSES FOR PROBE CARD ASSEMBLIES AND PACKAGES HAVING WAFER LEVEL SPRINGS
    4.
    发明专利
    CONSTRUCTION STRUCTURES AND MANUFACTURING PROCESSES FOR PROBE CARD ASSEMBLIES AND PACKAGES HAVING WAFER LEVEL SPRINGS 未知

    公开(公告)号：AU2003272205A1

    公开(公告)日：2004-01-06

    申请号：AU2003272205

    申请日：2003-06-23

    Applicant: NANONEXUS INC

    Inventor： MOK SAMMY ,  CHONG FU-CHIUNG ,  SWIATOWIEC FRANK ,  LAHIRI SYAMAL KUMAR ,  HAEMER JOSEPH MICHAEL

    IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H05K3/40 ,  H05K7/10

    Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.

    METHOD AND APPARATUS FOR PRODUCING CONTROLLED STRESSES AND STRESS GRADIENTS IN SPUTTERED FILMS
    5.
    发明申请
    METHOD AND APPARATUS FOR PRODUCING CONTROLLED STRESSES AND STRESS GRADIENTS IN SPUTTERED FILMS 审中-公开
    在溅射膜中产生受控应力和应力梯度的方法和设备

    公开(公告)号：WO2007011751B1

    公开(公告)日：2007-06-21

    申请号：PCT/US2006027423

    申请日：2006-07-14

    Applicant: NANONEXUS INC ,  GIAUQUE PIERRE H ,  CHONG FU CHIUNG ,  SWIATOWIEC FRANK ,  SMITH DONALD

    Inventor： GIAUQUE PIERRE H ,  CHONG FU CHIUNG ,  SWIATOWIEC FRANK ,  SMITH DONALD

    IPC: B05D5/12

    CPC classification number: C23C14/352 ,  C23C14/35 ,  H01J37/3408 ,  H01J37/3447 ,  H01J37/347

    Abstract: An enhanced sputtered film processing system and method comprises one or more sputter deposition sources each having a sputtering target surface and one or more side shields, to increase the relative collimation of the sputter deposited material, such as about the periphery of the sputtering target surface, toward workpiece substrates. One or more substrates are provided, wherein the substrates have a front surface and an opposing back surface, and may have previously applied layers, such as adhesion or release layers. The substrates and the deposition targets are controllably moved with respect to each other. The relatively collimated portion of the material sputtered from the sputtering target surface travels beyond the side shields and is deposited on the front surface of the substrates. The increase in relative collimation results in deposited films with desirable properties of readily controllable compressive stress and mechanical integrity without the use of ion bombardment.

    Abstract translation: 增强的溅射膜处理系统和方法包括一个或多个溅射沉积源，每个溅射沉积源具有溅射靶表面和一个或多个侧部屏蔽，以增加溅射沉积材料的相对准直，例如围绕溅射靶表面的周边， 朝向工件基材。 提供一个或多个衬底，其中衬底具有前表面和相对的后表面，并且可以具有先前施加的层，例如粘附层或释放层。 衬底和沉积目标可控制地相对于彼此移动。 从溅射靶表面溅射的材料的相对准直部分行进超出侧屏蔽并沉积在基板的前表面上。 相对准直度的增加导致所沉积的膜具有易于控制的压缩应力和机械完整性的理想特性，而无需使用离子轰击。

    CONSTRUCTION STRUCTURES AND MANUFACTURING PROCESSES FOR PROBE CARD ASSEMBLIES AND PACKAGES HAVING WAFER LEVEL SPRINGS
    7.
    发明申请
    CONSTRUCTION STRUCTURES AND MANUFACTURING PROCESSES FOR PROBE CARD ASSEMBLIES AND PACKAGES HAVING WAFER LEVEL SPRINGS 审中-公开
    用于探头组件的构造和制造工艺和具有水平水平弹簧的包装

    公开(公告)号：WO2004001807A3

    公开(公告)日：2004-12-23

    申请号：PCT/US0319963

    申请日：2003-06-23

    Applicant: NANONEXUS INC

    Inventor： MOK SAMMY ,  CHONG FU-CHIUNG ,  SWIATOWIEC FRANK ,  LAHIRI SYAMAL KUMAR ,  HAEMER JOSEPH MICHAEL

    IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H05K3/40 ,  H05K7/10 ,  G01R31/02

    CPC classification number: G01R1/07378 ,  G01R1/06716 ,  G01R1/06727 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/2889 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4092 ,  H05K7/1061 ,  Y10S439/912

    Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.

    Abstract translation: 公开了增强的集成电路探针卡和封装组件的几个实施例，其延伸了MEMS和薄膜制造的探针的机械顺应性，使得这些类型的弹簧探针结构可用于测试半导体上的一个或多个集成电路 晶圆。 公开了在商业晶片探测设备中提供紧密的信号垫间距顺应性和/或实现高水平并行测试的探针卡组件的几个实施例。 在一些优选实施例中，探针卡组件结构包括可分离的标准部件，这降低了组装制造成本和制造时间。 这些结构和组件能够以晶圆形式进行高速测试。 这些探头还内置了集成电路和MEMS或薄膜制造的弹簧尖端和基板上的探针布局结构的机械保护。 替代卡组合结构包括柔性载体结构，例如粘贴到探针芯片基底上的贴花或屏幕。

    METHOD AND APPARATUS FOR PRODUCING CONTROLLED STRESSES AND STRESS GRADIENTS IN SPUTTERED FILMS
    10.
    发明申请
    METHOD AND APPARATUS FOR PRODUCING CONTROLLED STRESSES AND STRESS GRADIENTS IN SPUTTERED FILMS 审中-公开
    在溅射膜中生产受控应力和应力梯度的方法和装置

    公开(公告)号：WO2007011751A2

    公开(公告)日：2007-01-25

    申请号：PCT/US2006027423

    申请日：2006-07-14

    Applicant: NANONEXUS INC ,  GIAUQUE PIERRE H ,  CHONG FU CHIUNG ,  SWIATOWIEC FRANK ,  SMITH DONALD

    Inventor： GIAUQUE PIERRE H ,  CHONG FU CHIUNG ,  SWIATOWIEC FRANK ,  SMITH DONALD

    IPC: H01L21/203

    CPC classification number: C23C14/352 ,  C23C14/35 ,  H01J37/3408 ,  H01J37/3447 ,  H01J37/347

    Abstract: An enhanced sputtered film processing system and associated method comprises one or more sputter deposition sources each having a sputtering target surface and one or more side shields extending therefrom, to increase the relative collimation of the sputter deposited material, such as about the periphery of the sputtering target surface, toward workpiece substrates. One or more substrates are provided, wherein the substrates have a front surface and an opposing back surface, and may have one or more previously applied layers, such as an adhesion or release layer. The substrates and the deposition targets are controllably moved with respect to each other. The relatively collimated portion of the material sputtered from the sputtering target surface travels beyond the side shields and is deposited on the front surface of the substrates. The increase in relative collimation results in deposited films with desirable properties including but not limited to high levels of both readily controllable compressive stress and mechanical integrity without the use of ion bombardment.

    Abstract translation: 增强的溅射膜处理系统和相关方法包括一个或多个溅射沉积源，每个溅射沉积源具有溅射靶表面和从其延伸的一个或多个侧屏蔽，以增加溅射沉积材料的相对准直，例如大约溅射周边 目标表面，朝向工件基板。 提供一个或多个基底，其中基底具有前表面和相对的后表面，并且可以具有一个或多个预先施加的层，例如粘附或释放层。 基板和沉积靶相对于彼此可控地移动。 从溅射靶表面溅射的材料的相对准直的部分超过侧面屏蔽并沉积在基板的前表面上。 相对准直的增加导致具有期望性能的沉积膜，包括但不限于高水平的易于控制的压缩应力和机械完整性，而不使用离子轰击。

Patent Agency Ranking