公开(公告)号：US20210091020A1

公开(公告)日：2021-03-25

申请号：US16576757

申请日：2019-09-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01L23/00

Abstract: An integrated circuit structure includes a substrate, a metal pad, a first passivation layer, a second passivation layer, and a conductive bump. The metal pad is over the substrate. The metal pad includes a probing portion and a bumping portion laterally connected to the probing region. The first passivation layer is over the metal pad. The second passivation layer is over the first passivation layer and has an opening. The bumping portion is in the opening. The conductive bump is in the opening of the second passivation layer and contacts the probing portion. The probing portion and the conductive bump are separated by the first passivation layer.

公开(公告)号：US20250014824A1

公开(公告)日：2025-01-09

申请号：US18889659

申请日：2024-09-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01G4/228 ,  H01G13/00 ,  H01L29/94 ,  H10B12/00

Abstract: A capacitor structure includes a contact layer having first, second, third, fourth and fifth portions arranged from periphery to center, an insulating layer over the contact layer and having an opening exposing the contact layer, a bottom conductive plate in the opening, a dielectric layer conformally on the bottom conductive plate and contacting the second and fourth portions of the contact layer, and a top conductive plate on the dielectric layer. The bottom conductive plate includes first, second and third portions extending along a depth direction of the opening, separated from each other, and contacting the first, third and fifth portions of the contact layer, respectively. The first portion of the bottom conductive plate surrounds the second portion of the bottom conductive plate, and the second portion of the bottom conductive plate surrounds the third portion of the bottom conductive plate.

公开(公告)号：US20240258220A1

公开(公告)日：2024-08-01

申请号：US18631072

申请日：2024-04-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2924/1533

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.

公开(公告)号：US20220375837A1

公开(公告)日：2022-11-24

申请号：US17324101

申请日：2021-05-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.

公开(公告)号：US20230268258A1

公开(公告)日：2023-08-24

申请号：US18305374

申请日：2023-04-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2924/1533

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.

公开(公告)号：US20230245826A1

公开(公告)日：2023-08-03

申请号：US18193653

申请日：2023-03-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01G4/228 ,  H01G13/00 ,  H01L29/94 ,  H10B12/00

CPC classification number: H01G4/228 ,  H01G13/00 ,  H01L29/945 ,  H10B12/37 ,  H10B12/038 ,  H10B12/39

Abstract: A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.

公开(公告)号：US20220351908A1

公开(公告)日：2022-11-03

申请号：US17242327

申请日：2021-04-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01G4/228 ,  H01G13/00 ,  H01G4/005

Abstract: A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

公开(公告)号：US20220139710A1

公开(公告)日：2022-05-05

申请号：US17090869

申请日：2020-11-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01L21/033 ,  H01L21/768

Abstract: A method of forming a patterned hard mask includes: forming first photoresist features on a hard mask layer; forming at least one sacrificial feature between immediately-adjacent two of the first photoresist features on the hard mask layer; performing a trimming process to the first photoresist features to form second photoresist features; and using the at least one sacrificial feature and the second photoresist features as etching mask, and performing a first etching process to the hard mask layer, in which a plurality of trenches are formed in the hard mask layer to obtain the patterned hard mask.