公开(公告)号：US20240410934A1

公开(公告)日：2024-12-12

申请号：US18808239

申请日：2024-08-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei Zhong LI ,  Hsih-Yang CHIU

IPC: G01R31/28 ,  G01R1/067 ,  G01R1/073

Abstract: A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

公开(公告)号：US20240321942A1

公开(公告)日：2024-09-26

申请号：US18675156

申请日：2024-05-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih KANG ,  Hsih-Yang CHIU

IPC: H01G4/30 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L23/5223

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US20240090208A1

公开(公告)日：2024-03-14

申请号：US17930416

申请日：2022-09-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei Zhong LI ,  Hsih-Yang CHIU

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: A semiconductor structure includes a substrate, an anti-fuse, first and second transistors, a contact structure, and a dielectric layer. The substrate includes a well region and first and second conductivity type doped regions in the well region, in which the second conductivity type doped region surrounds the first conductivity type doped region and includes a first portion and a second portion perpendicular to the first portion in a top view. The anti-fuse is in an anti-fuse region of the first conductivity type doped region. The first and second transistors are in the well region. The anti-fuse is disposed between the first and second transistors, and the anti-fuse is electrically connected to the first and second transistors. The contact structure is above the anti-fuse. The dielectric layer is between the contact structure and the anti-fuse region of the first conductivity type doped region.

公开(公告)号：US20230326956A1

公开(公告)日：2023-10-12

申请号：US18333507

申请日：2023-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih KANG ,  Hsih-Yang CHIU

IPC: H01L21/02 ,  H01G4/30 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01G4/30

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US20220310580A1

公开(公告)日：2022-09-29

申请号：US17212620

申请日：2021-03-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang CHIU

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L25/065

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

公开(公告)号：US20220139710A1

公开(公告)日：2022-05-05

申请号：US17090869

申请日：2020-11-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01L21/033 ,  H01L21/768

Abstract: A method of forming a patterned hard mask includes: forming first photoresist features on a hard mask layer; forming at least one sacrificial feature between immediately-adjacent two of the first photoresist features on the hard mask layer; performing a trimming process to the first photoresist features to form second photoresist features; and using the at least one sacrificial feature and the second photoresist features as etching mask, and performing a first etching process to the hard mask layer, in which a plurality of trenches are formed in the hard mask layer to obtain the patterned hard mask.

公开(公告)号：US20220059553A1

公开(公告)日：2022-02-24

申请号：US17451160

申请日：2021-10-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang CHIU

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525

Abstract: A memory cell includes a semiconductor substrate, a transistor, and a first anti-fuse structure. The transistor is above the semiconductor substrate. The first anti-fuse structure is above the semiconductor substrate and adjacent the transistor, and includes a first terminal and a second terminal. The first terminal of the first anti-fuse structure is in the semiconductor substrate and laterally surrounds the transistor. The second terminal of the first anti-fuse structure is above and spaced apart from the first terminal of the first anti-fuse structure.

公开(公告)号：US20220059435A1

公开(公告)日：2022-02-24

申请号：US17453343

申请日：2021-11-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin SHIH ,  Hsih-Yang CHIU ,  Ching-Hung CHANG ,  Pei-Jhen WU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

公开(公告)号：US20200176358A1

公开(公告)日：2020-06-04

申请号：US16281360

申请日：2019-02-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang CHIU

IPC: H01L23/48 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.

公开(公告)号：US20200152600A1

公开(公告)日：2020-05-14

申请号：US16186100

申请日：2018-11-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang CHIU

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768

Abstract: The present disclosure provides a method of manufacturing stacked wafers. The method includes receiving a first wafer having semiconductor components formed therein; receiving a second wafer having semiconductor components formed therein; attaching the first wafer to the second wafer; and forming a set of stacked wafers by thinning the second wafer, using the first wafer as a holder.