公开(公告)号：US20240395762A1

公开(公告)日：2024-11-28

申请号：US18201319

申请日：2023-05-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/00

Abstract: A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

公开(公告)号：US20240363454A1

公开(公告)日：2024-10-31

申请号：US18239231

申请日：2023-08-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L21/66 ,  G01R31/28 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L21/78 ,  H01L24/05 ,  H01L2224/05553

Abstract: A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

公开(公告)号：US20240203887A1

公开(公告)日：2024-06-20

申请号：US18379873

申请日：2023-10-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L23/13 ,  H01L23/3121 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second electronic component and a second substrate. The first electronic component is disposed over and electrically connected to the first substrate. An active surface of the first electronic component faces the first substrate. The second electronic component is disposed under and electrically connected to the first substrate. An active surface of the second electronic component faces the first substrate. The second substrate is disposed under and electrically connected to the first substrate. The second substrate defines a cavity for accommodating the second electronic component.

公开(公告)号：US20240178083A1

公开(公告)日：2024-05-30

申请号：US18368128

申请日：2023-09-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/3201 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32235 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/2027

Abstract: A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

公开(公告)号：US20240170410A1

公开(公告)日：2024-05-23

申请号：US18056549

申请日：2022-11-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L22/32 ,  H01L23/5381 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/48132

Abstract: A memory device package and a method of manufacturing a memory device package. The memory device package includes a substrate having a first chip region, a second chip region, and a first scribe line region connected between the first chip region and the second chip region. The memory device package also includes a first memory chip disposed over the first chip region and a second memory chip disposed over the second chip region.

公开(公告)号：US20240021551A1

公开(公告)日：2024-01-18

申请号：US18197825

申请日：2023-05-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/48 ,  H01L24/03 ,  H01L2224/05083 ,  H01L2924/182 ,  H01L2224/48464 ,  H01L2924/35121 ,  H01L2924/15151 ,  H01L2224/03416 ,  H01L2224/05557 ,  H01L2224/05573 ,  H01L2224/05017 ,  H01L2224/05076 ,  H01L2924/15311 ,  H01L2224/48644 ,  H01L2224/0239 ,  H01L2224/05155 ,  H01L2224/03452 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/48221 ,  H01L2224/0362 ,  H01L2224/02331 ,  H01L2224/05644 ,  H01L2224/05548 ,  H01L2224/05008 ,  H01L2224/05147

Abstract: A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

公开(公告)号：US20230369306A1

公开(公告)日：2023-11-16

申请号：US17743044

申请日：2022-05-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L24/92 ,  H01L2224/92147 ,  H01L2224/9211

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.

公开(公告)号：US20230366910A1

公开(公告)日：2023-11-16

申请号：US17742546

申请日：2022-05-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: G01R1/04 ,  H01R12/85 ,  G01R31/28

CPC classification number: G01R1/0466 ,  G01R31/2886 ,  G01R31/2896 ,  H01R12/85

Abstract: A testing device and a method for testing a semiconductor device are provided. The testing device includes a socket having a cavity for accommodating a device under test (DUT), and a cover disposed on the socket. The socket includes a thermal conductive material. The cover includes a plate, a circuit board attached to the plate, and an opening penetrating the plate and the circuit board, exposing the cavity of the socket.

公开(公告)号：US20230361073A1

公开(公告)日：2023-11-09

申请号：US17739415

申请日：2022-05-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/3128 ,  H01L21/563 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2224/92165 ,  H01L2224/3224 ,  H01L2224/33055 ,  H01L2224/3303 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29386 ,  H01L2224/06166 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/4846 ,  H01L2224/48464 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48091 ,  H01L2224/49097 ,  H01L2224/49052 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2924/15151 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: A method of manufacturing a WBGA package includes providing a carrier having a first surface and a second surface opposite to the first surface of the carrier, wherein the carrier has a through hole extending between the first surface and the second surface of the carrier; disposing an electronic component on the second surface of the carrier, wherein the electronic component includes a first bonding pad and a second bonding pad; and electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

公开(公告)号：US20230361012A1

公开(公告)日：2023-11-09

申请号：US17739427

申请日：2022-05-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L21/565 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/182 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73215 ,  H01L2224/48101 ,  H01L2224/48229 ,  H01L2224/49177 ,  H01L2224/49175 ,  H01L2224/4917 ,  H01L2224/06132 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05573 ,  H01L2224/05578

Abstract: A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a carrier having a first surface and a second surface opposite to the first surface of the carrier. The carrier has a through hole filled with a first package body and extending between the first surface and the second surface of the carrier. The WBGA package also includes an electronic component disposed on the second surface of the carrier. The electronic component includes a first bonding pad and a second bonding pad. The WBGA package also includes a first bonding wire electrically connected between the first bonding pad and the second bonding pad.