公开(公告)号：JPH06231096A

公开(公告)日：1994-08-19

申请号：JP1333693

申请日：1993-01-29

Applicant: NAT AEROSPACE LAB ,  FUJITSU LTD

Inventor： MIYOSHI HAJIME ,  FUKUDA MASAHIRO ,  IKEDA MASAYUKI ,  TAKAMURA MORIYUKI

IPC: G06F15/173 ,  G06F15/16

Abstract: PURPOSE:To realize a complete connection network among plural devices with out increasing the number of hardware regarding a complete connection type data transferring device. CONSTITUTION:A transfer processing part 16 of plural processors 10 rearranges data on a buffer corresponding to the data transfer and transmission destination, transmits the data by time-division, and performs access to a main storage according to information received from a network 12. The network 12 rearranges the data received by time-division from the plural processors 10, and transmits the data to each transmission destination. For example, when the network 12 is constituted of a cross bar network, the (n) processors 10 are connected with the network 12, and proper device number 0, 1, 2,..., n-1 is assigned to each processor 10, the transfer processing part 16 transmits transmission data for the arbitrary transmission destination processor by shifting only by its own device number (i), and the network 12 executes the connection to the processor 10 made to the device number k=i+j from the processor 10 of the device (i) at a timing (j).

公开(公告)号：JPH06202947A

公开(公告)日：1994-07-22

申请号：JP28014092

申请日：1992-10-19

Applicant: NAT AEROSPACE LAB

Inventor： ISOBE TOSHIO ,  FUKUDA MASAHIRO

IPC: G06F12/02 ,  G06F12/00 ,  G06F12/08 ,  G06F13/16

Abstract: PURPOSE:To provide a buffer memory controller which has high universal applicability and can facilitate the input/output of data subject to the signals of all standards by providing several pairs of data transfer control circuits and buffer memories in parallel to each other. CONSTITUTION:A clock pulse generator 46 is controlled by the synchronizing signal supplied from a computer main body 1 or an external device 3 and produces the clock pulses. A counter register 45 stores the memory address of the data stored in a buffer memory 42 and to be read and written secures synchronization with the clock pulse of the generator 46 to control the largest count value through the main body 1 or the device 3. A data transfer controller (a) 41 controls the input/output of data between the main body 1 and the memory 42, and a data transfer controller (b) 44 refers to the value of the register 45 as a memory address and reads and writes the data stored in the memory 42.

公开(公告)号：JPH06301650A

公开(公告)日：1994-10-28

申请号：JP5118693

申请日：1993-03-12

Applicant: NAT AEROSPACE LAB ,  FUJITSU LTD

Inventor： MIYOSHI HAJIME ,  FUKUDA MASAHIRO ,  IKEDA MASAYUKI ,  TAKAMURA MORIYUKI

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/173 ,  H04L12/701 ,  H04L12/721 ,  H04L12/56

Abstract: PURPOSE:To simplify a communication procedure and to reduce the overhead of processing by efficiently executing repeating transfer through other processors in a data transfer repeating mechanism for mutually executing data communication through other processors among processors provided in a data processing system such as a parallel computer system. CONSTITUTION:Each of plural processors 10-1 to 10-n is provided with a data transfer control part 26 for specifying the device numbers of one or more through processors in addition to the device number of the final destination processor in the heater part of a transmission packet and returning a receiving packet to a network 12 by setting up the next through processor to the next destination without processing body data at the time of detecting that its own processor is not the final destination processor based upon device numbers in the header data of the receiving packet or returning the packet to a network 12 by setting up the final destination processor to the next destination when there is not next through processor.

公开(公告)号：JPH06231101A

公开(公告)日：1994-08-19

申请号：JP1333793

申请日：1993-01-29

Applicant: NAT AEROSPACE LAB ,  FUJITSU LTD

Inventor： MIYOSHI HAJIME ,  FUKUDA MASAHIRO ,  IKEDA MASAYUKI ,  TAKAMURA MORIYUKI

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/173

Abstract: PURPOSE:To monitor the time of a packet unreceivable state due to the invalidation of a receiving butter and to evade system abnormality such as network hanging in respect to a receiving time-out detecting mechanism to be used for communication processing between plural processors in a data processing system such as a parallel computer system. CONSTITUTION:A comparing means 45 compares and judges the updating value of a receiving timer 50 for measuring the time of the invalidated state of the receiving buffer 45 in a main storage part 16, and at the time of detecting the arrival of an updated result at a specific value, generates an interruption to an instruction processing part 14 to execute processing for separating a processor 10 from a switching circuit in a network 12. The means 54 detects the updated result of the timer 50 at two stages specified by the 1st and 2nd specific values and executes processing so as to generate an interruption to the processing part 14 at the time of detecting arrival at the 1st specific value and separate the processor 10 concerned from the switching circuit of the network 12 at the time of detecting arrival at the 2nd specific value.

公开(公告)号：JPH06110854A

公开(公告)日：1994-04-22

申请号：JP19325491

申请日：1991-08-01

Applicant: NAT AEROSPACE LAB

Inventor： ISOBE TOSHIO ,  FUKUDA MASAHIRO ,  NAKAMURA TAKASHI

IPC: G06F13/16 ,  G06F15/16 ,  G06F15/167

Abstract: PURPOSE:To provide a new digital computer system which can simultaneously process plural programs in parallel with each other and at a high speed. CONSTITUTION:An arithmetic processor 11 is provided to serve as a host processor together with the arithmetic processing elements 12a and 12b surrounding the processor 11, and the memory banks 14 which are usually connected to the bus lines of both elements 12a and 12b and then can be connected to the bus line of the processor 11 after the separation from the bus lines of the elements 12a and 12b by a switch 13. The switch 13 functions to connect the banks 14 o the host arithmetic processor or an arithmetic processor. Then a controller 15 is added to control the switch 13 through the host arithmetic processor. In such a constitution, a parallel computer is obtained.