公开(公告)号：JP2001056649A

公开(公告)日：2001-02-27

申请号：JP23094899

申请日：1999-08-17

Applicant: NEC CORP

Inventor： ARAI NOBUHIRO

IPC: G09F9/00 ,  G02F1/13 ,  G02F1/1335 ,  G02F1/13357 ,  G02F1/1345

Abstract: PROBLEM TO BE SOLVED: To make it possible to provide liquid crystal display device which is more inexpensive and light in weight by decreasing the number of substrate layers, thereby enabling the use of an inexpensive standard-length substrate material. SOLUTION: A conductive layer 2 is formed on the front surface of a reflection plate 1 by vacuum vapor deposition, electroplating, etc., by which both functions of 'reflection of light' and 'electrical conduction' may be embodied with one part. The conductive layer 2 is connected via a contact member 5 disposed at the ground pattern of a printed circuit board 4 and may be utilized as a ground layer. Consequently, the need for the ground layer of the printed circuit board 4 is eliminated.

公开(公告)号：JPH10333604A

公开(公告)日：1998-12-18

申请号：JP13734797

申请日：1997-05-28

Applicant: NEC CORP

Inventor： SASAKI HIDEKI ,  NAKAJIMA KEIICHI ,  ARAI NOBUHIRO ,  HORI MASAHARU ,  HARADA TAKASHI

IPC: G01R29/08 ,  G01R31/00 ,  G09F9/35

Abstract: PROBLEM TO BE SOLVED: To provide a liquid crystal module driving device that can restrain unnecessary electromagnetic waves from a signal source for driving the liquid crystal module, and also than can easily change the connecting condition of the module gland and the signal-source glad. SOLUTION: Since a signal source 2 for driving a liquid crystal module 4 is housed in a conductive case made of a metal or the like, unnecessary electromagnetic waves from the signal source are restrained. The case is provided with a module fixing jig 3 for insertedly fixing the liquid crystal module 4, so that the gland electrode of the liquid crystal module 4 is easily and electrically connected to the gland electrode of the signal source 2. In the case where the respective electrodes of the glands are to be electrically separated from each other, it will do a nonconductive sheet is inserted. Thereby, the unnecessary electromagnetic wave characteristic taken the gland connection into consideration can be easily evaluated.

公开(公告)号：JP2005339122A

公开(公告)日：2005-12-08

申请号：JP2004156114

申请日：2004-05-26

Applicant: Nec Corp ,  日本電気株式会社

Inventor： ARAI NOBUHIRO

IPC: G06F17/50 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To suppress the bending or deformation of a multilayered substrate when sending the multilayered substrate flow to a reflow furnace, and soldering parts to the multilayered substrate.
SOLUTION: Designation, related to the layer structure of plate-shaped articles, is received by a layer structure designating means 1. A layer structure examining means 2 examines whether the layer structure is symmetrical with respect to the center line showing the middle of the plate thickness of the plate-shaped articles, having the layer structure designated by the layer structure designating means 1 on the cross-section of the plate thickness direction of the plate-shaped articles.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了抑制多层基板在将多层基板流送到回流炉时的弯曲或变形，以及将部件焊接到多层基板上。 解决方案：与板状物品的层结构相关的指定由层结构指定装置1接收。层结构检查装置2检查层结构是否相对于显示中间的中心线对称 在板状制品的板厚方向的横截面上具有由层结构指定装置1指定的层结构的板状制品的板厚。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2010205825A

公开(公告)日：2010-09-16

申请号：JP2009048023

申请日：2009-03-02

Applicant: Nec Corp ,  日本電気株式会社

Inventor： ARAI NOBUHIRO

IPC: H05K1/11 ,  H05K1/02

Abstract: PROBLEM TO BE SOLVED: To stabilize the operation of a circuit formed on a printed wiring board in the printed wiring board with a conductor pattern to be connected with an electrode terminal provided in an inner layer of a card edge.
SOLUTION: The card edge 2 includes the electrode terminal 11a formed on its front surface, the first conductor pattern 12a formed inner than the electrode terminal 11a and connected with the electrode terminal 11a, the second conductor pattern 15a formed inner than the first conductor pattern 12a, and a ground pattern 13a formed between the first conductor pattern 12a and the second conductor pattern 15a.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了稳定印刷电路板中形成在印刷电路板上的电路的操作，其中导体图案将与设置在卡边缘的内层中的电极端子连接。 解决方案：卡缘2包括形成在其前表面上的电极端子11a，第一导体图案12a形成在电极端子11a的内部并与电极端子11a连接，第二导体图案15a形成在第一 导体图案12a和形成在第一导体图案12a和第二导体图案15a之间的接地图案13a。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2011133990A

公开(公告)日：2011-07-07

申请号：JP2009291136

申请日：2009-12-22

Applicant: Nec Corp ,  日本電気株式会社

Inventor： ARAI NOBUHIRO

IPC: G06F17/50 ,  H05K3/00

Abstract: PROBLEM TO BE SOLVED: To solve such a problem that voltage drop of a power supply line pattern 12 is not easily detected in designing a circuit pattern in a printed wiring board.
SOLUTION: A voltage drop calculation part 35 which calculates the voltage drop of power supply line based on a power supply line pattern extracted from a circuit pattern created based on information related with circuit arrangement including signal wiring, power supply line, vias, clearance holes and components configuring a printed circuit board defines a value calculated by subtracting a value calculated by totaling the diameters of the clearance holes aligned in a row vertical to a direction in which currents existing in the power supply line pattern are running from the width of the power supply line pattern as the valid wiring width of the power supply line pattern, and calculates the voltage drop of the power supply line by calculating the resistance value of the power supply line based on the valid wiring width of the power supply line pattern.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 解决的问题为了解决在设计印刷电路板中的电路图案时不容易检测到电源线图案12的电压降的问题。 解决方案：一种电压降计算部分35，其基于从基于与包括信号布线，电源线，通孔的电路布置有关的信息产生的电路图案提取的电源线图案来计算电源线的电压降， 构成印刷电路板的间隙孔和部件定义了通过减去通过将与在电源线图案中存在的电流正在行进的垂直方向排列的排列孔的直径相乘而计算出的值， 电源线图案作为电源线图案的有效布线宽度，并且通过基于电源线图案的有效布线宽度计算电源线的电阻值来计算电源线的电压降。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008016470A

公开(公告)日：2008-01-24

申请号：JP2006183025

申请日：2006-07-03

Applicant: Aica Kogyo Co Ltd ,  Nec Corp ,  アイカ工業株式会社 ,  日本電気株式会社

Inventor： ARAI NOBUHIRO ,  TANAKA AKIHIRO

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0234 ,  H05K1/0231 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/10022 ,  H05K2201/10159

Abstract: PROBLEM TO BE SOLVED: To achieve stable operation of a high-speed DRAM in a printed circuit board in which the high-speed DRAM and a memory controller are mounted. SOLUTION: In the printed wiring board 1 in which the high-speed DRAM 42 and the memory controller 41 are mounted; a serial connection circuit consisting of a capacitor 45 and a resistor 46 has almost the same resistance value as that of characteristic impedance of a VTT power supply pattern, and is provided between the VTT power supply pattern 20 as a connection destination of a parallel termination resistor 44 of a memory bus wiring 43 and a GND pattern 30. With this configuration, the serial connection circuit can consume a high-frequency noise generated or propagating in the VTT power supply pattern due to an operation between the high-speed DRAM and the memory controller 41. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了在安装有高速DRAM和存储器控制器的印刷电路板中实现高速DRAM的稳定操作。 解决方案：在安装有高速DRAM42和存储器控制器41的印刷电路板1中， 由电容器45和电阻46组成的串联电路具有与VTT电源图案的特性阻抗几乎相同的电阻值，并且设置在作为并联终端电阻的连接目的地的VTT电源图案20之间 44的存储器总线布线43和GND图案30.由于这种配置，串行连接电路可以消耗由于高速DRAM和存储器之间的操作而在VTT电源模式中产生或传播的高频噪声 控制器41.版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002311880A

公开(公告)日：2002-10-25

申请号：JP2001110814

申请日：2001-04-10

Applicant: NEC CORP

Inventor： ARAI NOBUHIRO

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H04N5/66

Abstract: PROBLEM TO BE SOLVED: To provide a picture display device capable of suppressing the increasing of the number of signal lines to be accompanied by the increase of the transfer rate of pixel data. SOLUTION: After a shift register 21 inputs a shift signal STH as a start pulse, the shift register outputs a timing pulse which becomes active for a time equivalent to one clock in synchronism with the rising of the first clock signal CLK from a terminal C1 to a data register and thereafter it successively outputs timing pulses from terminals C2 to C64 to data registers. Moreover, an inversion signal intPOL2 is generated by allowing a logical product gate AND2 to perform the ANDing of the Q output of an SR type flip-flop SRFF3 and a superimposition signal. The inversion signal is outputted to a data register. Then, the superimposition signal of the shift signal STH and the inversion signal POL2 which is to be shifted to the source driver of a post-stage is raised by allowing a logical sum gate OR1 to perform the ORing of the output of a logical product gate AND3 and the Q output of a D type flip-flop DFF64.

公开(公告)号：JPH1092490A

公开(公告)日：1998-04-10

申请号：JP24613196

申请日：1996-09-18

Applicant: NEC CORP

Inventor： ARAI NOBUHIRO

IPC: G11C16/02 ,  G11C16/04 ,  H01R12/77 ,  H01R12/79 ,  H01R9/09

Abstract: PROBLEM TO BE SOLVED: To reduce the impedance of a grand potential between a printed circuit board and a printed board, in a liquid crystal display device. SOLUTION: A contact piece at a printed circuit board 2 side covers the rear side of a stacking connector 3, and fitted to a ground pattern 21 to connect integarlly thereto, and it reinforces the printed circuit board 2, as well as composes a magnetic shield to the stacking connector 3. Furthermore, the contact piece 4 is jointed with a contact piece 5 at a printed board 1 side, so as to form a bypass of a grand potential to the gland pin of the stacking connector 3, and the impedance of the ground potential between the printed board 1 and the printed circuit board 2 is reduced.