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公开(公告)号：US20160191138A1
公开(公告)日：2016-06-30
申请号：US14587572
申请日：2014-12-31
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol
IPC: H04B7/08 , H04L27/152 , H04L7/00
CPC classification number: H04B7/0885 , G06F13/40 , H04B1/16 , H04B1/40 , H04L27/152
Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.
Abstract translation: 一种无线电接收机，包括：串行数据接口，被配置为从另一无线电接收机接收串行数据信号; 时钟/数据恢复电路，被配置为从所述串行数据信号产生时钟信号和数据信号; 以及无线电前端，被配置为从时钟/数据恢复电路接收时钟信号以产生接收信号; 以及信号组合电路，被配置为组合接收信号和数据信号。
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公开(公告)号：US09584209B2
公开(公告)日：2017-02-28
申请号：US14587572
申请日：2014-12-31
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol
IPC: H04B7/08 , H04L27/152 , G06F13/40 , H04B1/16
CPC classification number: H04B7/0885 , G06F13/40 , H04B1/16 , H04B1/40 , H04L27/152
Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.
Abstract translation: 一种无线电接收机，包括：串行数据接口，被配置为从另一无线电接收机接收串行数据信号; 时钟/数据恢复电路，被配置为从串行数据信号产生时钟信号和数据信号; 以及无线电前端，被配置为从时钟/数据恢复电路接收时钟信号以产生接收信号; 以及信号组合电路，被配置为组合接收信号和数据信号。
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公开(公告)号：US10003343B2
公开(公告)日：2018-06-19
申请号：US15404059
申请日：2017-01-11
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol , Marcel Van De Gevel
CPC classification number: H03L7/089 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/0331
Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.
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公开(公告)号：US20170214407A1
公开(公告)日：2017-07-27
申请号：US15404059
申请日：2017-01-11
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol , Marcel VAN DE Gevel
CPC classification number: H03L7/089 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/0331
Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.
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