公开(公告)号：US10003343B2

公开(公告)日：2018-06-19

申请号：US15404059

申请日：2017-01-11

Applicant: NXP B.V.

Inventor： Kaveh Kianush ,  Evert-Jan Pol ,  Marcel Van De Gevel

IPC: H03L7/089 ,  H04L7/033 ,  H03L7/099 ,  H03L7/08

CPC classification number: H03L7/089 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/10 ,  H04L7/033 ,  H04L7/0331

Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.