Abstract:
A method for the manufacture of an electronic circuit is provided. A substrate (10) is provided with an indexing means (14) and personality windows (16) by etching. An adhesive is deposited on one surface of the substrate (10) to coat at least those regions to be laminated to a metallic foil. The foil is bonded to the nonconductive substrate (10) and patterned into a plurality of circuit traces (22). These steps may be repeated a plurality of times for a multi-metal layer structure.
Abstract:
There is disclosed a package for housing an integrated circuit device having a metallic base component (12). The base component (12) is coated with a dielectric layer (42) and conductive circuit traces (22) are formed on this dielectric layer (42). External leads (32) are electrically interconnected (48) to an outer end (26) of the circuit traces (22) adjacent to the perimeter (28) of the metallic substrate (12). The external leads (32) extend along sidewalls (40) of the metallic substrate (12) terminating proximate to the opposing side (38) of the substrate (12). An electrically insulating material (50) is disposed between the external leads (32) and the sidewalls (40) of the metal substrate (12) providing electrical isolation. In a second embodiment of the invention, a single row of solder balls is disposed about the periphery of the metallic substrate and bonded to the outer ends of the circuit traces.
Abstract:
A multi-metal layer interconnect tape (30) is provided. The tape (30) is not supported by a dielectric carrier. A thin dielectric adhesive layer (22) separates at least two self supporting metal foil layers (11, 12). In one embodiment of the invention, conductive vias (20) electrically interconnect leads (14') formed in a first metal foil layer (11) with ground (18) and power (16) circuits formed in a second metal foil layer (12). The metal foil layers (11, 12) are in close proximity so the vias (20) have a low aspect ratio. The vias (20) may be readily coated with continuous film of a conductive metal (26) and are much easier to clean than conventional vias having significantly higher aspect ratios.
Abstract:
There is provided a metallic component (20) for an electronic package (40). The component (20) is coated with an electrically non-conductive layer (24) and has a plurality of conductive circuit traces (26) on a surface. The circuit traces (26) are soldered (34) directly to the input/output pads (18) of an integrated circuit device (10) and to a second plurality of circuit traces (50). The component (20) may include a heat sink to enhance dissipation of heat from the encapsulated integrated circuit device (10).
Abstract:
There is provided a lead frame (12) with enhanced adhesion to a polymer resin (28). The lead frame (12) is coated with a thin layer (20) containing chromium, zinc or a mixture of chromium and zinc. A mixture of chromium and zinc with the zinc-to-chromium ratio in excess of about 4:1 is most preferred. The coated lead frames (12) exhibit improved adhesion to a polymeric resin (28).
Abstract:
There is provided a composite material (10) particularly suited for electrical and electronic applications having a metallic core (12) with a desired surface (14) finish. An acicular superficial coating layer (16) having an apparent thickness of less than 27.5 nanometers is adjacent to at least a portion of the metallic core (12). The superficial coating layer (16) is removable from the metallic core (12) without appreciable change to the metallic core (12) surface (14) finish.
Abstract:
An electronic package (10) having improved thermal performance. In the case of a plastic (30) package, the inner ends (20) of the leads (18) of the lead frame are attached to a heat slug (12) by a high thermal conductivity material (32) such as solder or a polymeric material. In the case of a metal package, the inner ends of the leads of the lead frame are attached to the metal base component by a high thermal conductivity material.
Abstract:
There is provided an electronic package (70) where the package components (52, 54) define a cavity (56). A semiconductor device (16) and a portion (18) of a leadframe (20) occupy part of the cavity (56). Substantially the remainder of the cavity (56) is filled with a polymer (26) so that an outermost surface (74) of the polymer (26) is coplanar with a surface (76) of one of the package components (54).
Abstract:
There is disclosed a process for the assembly of an electronic package (30) in which the outer lead ends (14) of a leadframe (50) are solderable (38) to external circuitry (36) without the necessity of a tin or solder coat. An oxidation resistant layer (44) is deposited on the leadframe (50) prior to package (30) assembly. The oxidation resistant layer (44) is removed prior to outer lead (14) soldering (38) providing a clean, oxide free metallic surface (46) for soldering (38).
Abstract:
An electronic package having improved thermal performance. In the case of a plastic package, the inner ends of the leads of the lead frame are attached to a heat slug by a high thermal conductivity material such as solder or a polymeric material. In the case of a metal package, the inner ends of the leads of the leadframe are attached to the metal base component by a high thermal conductivity material.