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    TWO OR MORE LAYER PRINTED CIRCUIT ASSEMBLIES
    2.
    发明专利
    TWO OR MORE LAYER PRINTED CIRCUIT ASSEMBLIES 未知

    公开(公告)号：GB1249659A

    公开(公告)日：1971-10-13

    申请号：GB5373968

    申请日：1968-11-13

    Applicant: PHOTOCIRCUITS CORP

    Inventor： SCHNEBLE FREDERICK W ,  LEECH EDWARD ,  POLICHETTE JOSEPH

    IPC: H05K3/18 ,  H05K3/46

    Abstract: 1,249,659. Printed circuits. PHOTOCIRCUITS CORP. 13 Nov., 1968, No. 53739/68. Heading H1R. [Also in Division C7] In order to build up a multi-layer printed circuit assembly electrolessly plated printed circuit layers separated by insulating masks are sequentially formed simultaneously with electrolessly plated connecting pads in designated areas to form interconnections between the printed circuit layers. In the first embodiment, Fig. 1 a first circuit pattern 102 is formed on an insulating base 100 by a print and etch or electroless process and then a resin insulating mask 104 is screened over the whole of circuit pattern except in areas 103 which define interconnecting points between the circuit layers. An adhesive ink containing catalytic particles 106 is screened on the insulating mask 104 slightly overlapping areas 103 as at 107 and a second circuit pattern 108 electrolessly plated on the catalytic particles 106 together with a deposit 110 on pads 103. A connection is thus made between layers 102 and 108. As many layers and interconnections are deposited as required by repeating the steps. The first circuit pattern may be formed by depositing a layer of catalytic ink on the insulating substrate, Fig. 2 (not shown) in the form of the desired circuit pattern and then the circuit pattern is formed by electroless deposition. In the arrangement of Fig. 3 (not shown) the insulating base comprises a moulded resin base having dispersed therein finely divided particles of a catalytic agent and the first circuit pattern is formed by printing a negative insulating mask of the circuit pattern on the base and electrolessly plating the exposed areas. The second circuit pattern is formed on a non- conducting catalytic ink deposited on the first circuit pattern by printing a negative insulating mask on the catalytic ink and electrolessly plating. Alternatively the second circuit pattern may be formed by superimposing an insulating mask on the first circuit pattern, printing a positive pattern of the second circuit pattern on the mask with catalytic ink and electrolessly plating the second circuit pattern Fig. 4 (not shown). Various catalytic inks and base materials are described in which catalytic agents are dispersed in or coated on resin compounds together with copper electroless plating baths.

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