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Patent Agency Ranking
公开(公告)号：US09818913B2
公开(公告)日：2017-11-14
申请号：US15420705
申请日：2017-01-31
Applicant: Point Engineering Co., Ltd.
Inventor： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
CPC classification number: H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
Abstract: A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.
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2.发明授权公开(公告)号：US09595642B2
公开(公告)日：2017-03-14
申请号：US14753869
申请日：2015-06-29
Applicant: POINT ENGINEERING CO., LTD.
Inventor： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
CPC classification number: H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.
Abstract translation: 芯片基板包括层叠导电部分和层叠绝缘部分，其将导电部分与在芯片基板的上表面上包括绝缘部分的区域中的凹陷形状的腔体电隔离。 基板包括在上表面上的绝缘层，不包括空腔的区域，以及沿着绝缘层上的芯片基板的周边的连续镀层。 每个绝缘部分的顶表面的一部分暴露在空腔中，并且每个绝缘部分的顶表面的另一部分涂覆有绝缘层。 芯片封装包括芯片基板，光学元件通过密封构件或透镜密封在空腔中。
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公开(公告)号：US09913381B2
公开(公告)日：2018-03-06
申请号：US14460587
申请日：2014-08-15
Applicant: Point Engineering Co., Ltd.
Inventor： Bum Mo Ahn , Seung Ho Park , Kyoung Ja Yun
CPC classification number: H05K3/0052 , H01L33/48 , H01L33/62 , H01L2924/0002 , H05K1/183 , H05K2201/09718 , H05K2201/09827 , H05K2201/09845 , H05K2201/09854 , H05K2201/09863 , H05K2201/10 , H05K2201/10106 , H05K2201/10121 , Y10T29/49155 , H01L2924/00
Abstract: A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.
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公开(公告)号：US20170141274A1
公开(公告)日：2017-05-18
申请号：US15420705
申请日：2017-01-31
Applicant: Point Engineering Co., Ltd.
Inventor： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
CPC classification number: H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
Abstract: A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.
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5.发明申请公开(公告)号：US20150049447A1
公开(公告)日：2015-02-19
申请号：US14460587
申请日：2014-08-15
Applicant: Point Engineering Co., Ltd.
Inventor： Bum Mo Ahn , Seung Ho Park , Kyoung Ja Yun
CPC classification number: H05K3/0052 , H01L33/48 , H01L33/62 , H01L2924/0002 , H05K1/183 , H05K2201/09718 , H05K2201/09827 , H05K2201/09845 , H05K2201/09854 , H05K2201/09863 , H05K2201/10 , H05K2201/10106 , H05K2201/10121 , Y10T29/49155 , H01L2924/00
Abstract: A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.
Abstract translation: 防止在切割过程中产生的毛刺的基底基板包括：相对于基底基板沿一个方向堆叠的多个导电层; 至少一个绝缘层与所述导电层交替堆叠并电分离所述导电层; 以及根据所述芯片基板的预定区域，在切割所述基底基板期间，在所述切割面和所述绝缘层相接触的接触区域处覆盖所述绝缘层的通孔。 制造基底基板的方法包括交替地堆叠导电层和绝缘层并形成通孔。
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