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公开(公告)号：US09818913B2
公开(公告)日：2017-11-14
申请号：US15420705
申请日：2017-01-31
Applicant: Point Engineering Co., Ltd.
Inventor： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
CPC classification number: H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
Abstract: A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.
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2.发明授权公开(公告)号：US09595642B2
公开(公告)日：2017-03-14
申请号：US14753869
申请日：2015-06-29
Applicant: POINT ENGINEERING CO., LTD.
Inventor： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
CPC classification number: H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.
Abstract translation: 芯片基板包括层叠导电部分和层叠绝缘部分，其将导电部分与在芯片基板的上表面上包括绝缘部分的区域中的凹陷形状的腔体电隔离。 基板包括在上表面上的绝缘层，不包括空腔的区域，以及沿着绝缘层上的芯片基板的周边的连续镀层。 每个绝缘部分的顶表面的一部分暴露在空腔中，并且每个绝缘部分的顶表面的另一部分涂覆有绝缘层。 芯片封装包括芯片基板，光学元件通过密封构件或透镜密封在空腔中。
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公开(公告)号：US20170250333A1
公开(公告)日：2017-08-31
申请号：US15593726
申请日：2017-05-12
Applicant: Point Engineering Co., Ltd.
Inventor： Young Woon Jeon , Tae Hwan Song
IPC: H01L33/64 , H01L33/62 , H01L23/00 , H01L25/075
CPC classification number: H01L33/647 , H01L24/48 , H01L24/73 , H01L25/0753 , H01L33/486 , H01L33/62 , H01L33/644 , H01L2224/32225 , H01L2224/32245 , H01L2224/48139 , H01L2224/48227 , H01L2224/48505 , H01L2224/4911 , H01L2224/73265 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2924/00014 , H01L2924/10253 , H01L2924/12041 , H01L2924/181 , H05K1/0204 , H05K2201/10106 , H05K2201/10416 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
Abstract: The present invention relates to a substrate for an optical device, which is configured to connect an optical element substrate and an electrode substrate in a fitting manner, and simultaneously, to form one or more bridge pads which are insulated from the optical element substrate by a horizontal insulating layer, on the optical element substrate. The substrate for an optical device according to a first aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of an insulating material to form a conductive layer on at least a portion of the upper surface thereof, are connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; and a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate. The substrate for an optical device according to a second aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of a metal material to be connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate; and a fitting-type vertical insulating layer which is interposed between the optical element substrate and the electrode substrate so as to be connected to the fitting means.
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公开(公告)号：US20170141274A1
公开(公告)日：2017-05-18
申请号：US15420705
申请日：2017-01-31
Applicant: Point Engineering Co., Ltd.
Inventor： Ki Myung Nam , Young Woon Jeon , Kyoung Ja Yun
CPC classification number: H01L33/486 , H01L33/44 , H01L33/483 , H01L33/54 , H01L33/58 , H01L33/62 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066
Abstract: A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.
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