公开(公告)号：ES2383847T3

公开(公告)日：2012-06-26

申请号：ES08846869

申请日：2008-11-05

Applicant: QUALCOMM INC

Inventor： CASSIA MARCO ,  HADJICHRISTOS ARISTOTELE

IPC: H04B1/04

Abstract: Un aparato para suministrar una tensión a un circuito transmisor, procesando el circuito una señal para su transmisión por un canal de comunicaciones, comprendiendo el circuito transmisor un mezclador (104.1, 104.2) para trasladar una señal a una frecuencia más elevada, comprendiendo además el circuito transmisor un amplificador (104.5), comprendiendo el aparato: un módulo (202) de generación de tensión para generar una tensión (202a) de suministro para el circuito transmisor, estando la tensión de suministro a un primer nivel durante una primera fase, y a un segundo nivel durante una segunda fase, siendo el primer nivel más alto que el segundo nivel, siendo suministrada la tensión (202a) de suministro al mezclador del circuito transmisor.

公开(公告)号：WO2011014582A3

公开(公告)日：2011-05-26

申请号：PCT/US2010043593

申请日：2010-07-28

Applicant: QUALCOMM INC ,  CASSIA MARCO

Inventor： CASSIA MARCO

IPC: H03K17/06 ,  H03K17/0812

CPC classification number: H03K17/693 ,  H03K17/08122 ,  H03K17/102 ,  H03K2017/066 ,  H03K2217/0054

Abstract: Switches with variable control voltages and having improved reliability and performance are described. In an exemplary design, an apparatus includes a switch, a peak voltage detector, and a control voltage generator. The switch may be implemented with stacked transistors. The peak voltage detector detects a peak voltage of an input signal provided to the switch. In an exemplary design, the control voltage generator generates a variable control voltage to turn off the switch based on the detected peak voltage. In another exemplary design, the control voltage generator generates a variable control voltage to turn on the switch based on the detected peak voltage. In yet another exemplary design, the control voltage generator generates a control voltage to turn on the switch and attenuate the input signal when the peak voltage exceeds a high threshold.

Abstract translation: 描述了具有可变控制电压并具有改进的可靠性和性能的开关。 在示例性设计中，装置包括开关，峰值电压检测器和控制电压发生器。 开关可以用堆叠的晶体管来实现。 峰值电压检测器检测提供给开关的输入信号的峰值电压。 在示例性设计中，控制电压生成器基于检测到的峰值电压生成可变控制电压以关闭开关。 在另一示例性设计中，控制电压生成器基于检测到的峰值电压生成可变控制电压以导通开关。 在又一个示例性设计中，当峰值电压超过高阈值时，控制电压发生器产生控制电压以导通开关并衰减输入信号。

公开(公告)号：WO2011011639A3

公开(公告)日：2011-03-31

申请号：PCT/US2010042968

申请日：2010-07-22

Applicant: QUALCOMM INC ,  CASSIA MARCO

Inventor： CASSIA MARCO

IPC: H03K3/356 ,  H03K19/0185

CPC classification number: H03K3/35613 ,  H03K19/018528

Abstract: Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter (102) includes a driver circuit (110) and a latch (140). The driver circuit receives an input signal (Vinp, Vinn) having a first voltage range and provides a drive signal (Vdrp, Vdrn) having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal (Voutp, Voutn) having the second voltage range. The driver circuit may generate a control signal (Vctrip, Vctrin) having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.

Abstract translation: 描述了相对于输入和输出信号的电压摆幅具有低击穿电压的MOS晶体管实现的电平移位器和高电压逻辑电路。 在示例性设计中，电平移位器（102）包括驱动电路（110）和锁存器（140）。 驱动电路接收具有第一电压范围的输入信号（Vinp，Vinn），并提供具有第二电压范围的驱动信号（Vdrp，Vdrn）。 第一和第二电压范围可以覆盖正电压或负电压或不同的正电压范围。 闩锁接收驱动信号并提供具有第二电压范围的输出信号（Voutp，Voutn）。 驱动器电路可以基于输入信号产生具有完整电压范围的控制信号（Vctrip，Vctrin），然后可以基于控制信号产生驱动信号。 电平移位器可用于实现高压逻辑电路。

公开(公告)号：WO2010108039A8

公开(公告)日：2011-01-13

申请号：PCT/US2010027868

申请日：2010-03-18

Applicant: QUALCOMM INC ,  CASSIA MARCO ,  SAHOTA GURKANWAL SINGH

Inventor： CASSIA MARCO ,  SAHOTA GURKANWAL SINGH

IPC: H03F1/22 ,  H03F1/52 ,  H03F3/21 ,  H03F3/72 ,  H03G1/00

CPC classification number: H03F1/223 ,  H03F1/523 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2203/7206 ,  H03F2203/7215 ,  H03F2203/7236 ,  H03G1/0088

Abstract: A cascode amplifier (300) with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel (310a, 310b, 310k), with at least one branch being switchable between "on" and "off states. Each switchable branch includes a gain transistor (312) coupled to a cascode transistor (314). The gain transistor (312) amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor (314) buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor (312) and the cascode transistor (314) in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor (312) and shorting the gate and source of the cascode transistor (314).

Abstract translation: 描述了具有保护电路的共源共栅放大器（300）。 在一个示例性设计中，放大器包括并联耦合的多个分支（310a，310b，310k），其中至少一个分支可在“导通”和“关闭”状态之间切换。每个可切换支路包括一个增益晶体管（312） 级联晶体管（314），增益晶体管（312）放大输入信号并提供处于导通状态的放大信号，并且不将输入信号放大到截止状态，共源共栅晶体管（314）缓冲放大信号， 输出信号在导通状态下，输出信号摆幅可以在保护电路处于导通和截止状态下在增益晶体管（312）和共源共栅晶体管（314）之间分开，然后每个晶体管可观察到电压的一部分 断开状态下的分压可以通过使增益晶体管（312）浮置并使共栅二极管（314）的栅极和源极短路来实现。

公开(公告)号：WO2011031540A2

公开(公告)日：2011-03-17

申请号：PCT/US2010046915

申请日：2010-08-27

Applicant: QUALCOMM INC ,  SU WENJUN ,  HADJICHRISTOS ARISTOTELE ,  CASSIA MARCO ,  NARATHONG CHIEWCHARN

Inventor： SU WENJUN ,  HADJICHRISTOS ARISTOTELE ,  CASSIA MARCO ,  NARATHONG CHIEWCHARN

IPC: G01R19/04

CPC classification number: G01R19/04

Abstract: A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.

Abstract translation: 描述具有可变偏置电流和/或可变偏置电压的高线性快速峰值检测器。 在示例性设计中，峰值检测器包括晶体管，可变电流源，电容器和反馈电路。 晶体管接收输入信号并提供源极电流。 可变电流源接收输入信号，当输入信号为低电平时提供高偏置电流，并且当输入信号为高电平时提供低偏置电流。 当输入信号为高电平时，电容器由电源电流充电，当输入信号为低电平时，电容器被高偏置电流放电。 当输入信号为高电平时，反馈电路接收来自电容器的检测信号，并为晶体管提供更高的偏置电压，这导致来自晶体管的较高的源极电流。

公开(公告)号：WO2009061835A2

公开(公告)日：2009-05-14

申请号：PCT/US2008082504

申请日：2008-11-05

Applicant: QUALCOMM INC ,  CASSIA MARCO ,  HADJICHRISTOS ARISTOTELE ,  DONOVAN CONOR ,  LEE SANG-OH

Inventor： CASSIA MARCO ,  HADJICHRISTOS ARISTOTELE ,  DONOVAN CONOR ,  LEE SANG-OH

IPC: H03K17/693 ,  H03K17/0814 ,  H03K17/16

CPC classification number: H03K17/693 ,  Y10T307/696 ,  Y10T307/747

Abstract: A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor configured to select a first voltage supply, a second transistor configured to select a second voltage supply, a first parasitic current inhibitor coupled the first transistor, the first voltage supply, and the second voltage supply, where the first parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor, and a second parasitic current inhibitor coupled the second transistor, the first voltage supply, and the second voltage supply, where the second parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor.

Abstract translation: 提出了从多个电压源中选择电源电压的电路。 该电路包括：第一晶体管，被配置为选择第一电压源;第二晶体管，被配置为选择第二电压源;耦合第一晶体管，第一电压源和第二电压源的第一寄生电流抑制器，其中第一寄生 电流抑制器自动地利用提供最高电压的电压源来防止衬底电流流过第一晶体管的体节点，以及耦合第二晶体管，第一电压源和第二电压源的第二寄生电流抑制器，其中 第二寄生电流抑制器自动利用提供最高电压的电压源来防止衬底电流流过第二晶体管的体节点。

公开(公告)号：WO2011011638A2

公开(公告)日：2011-01-27

申请号：PCT/US2010042967

申请日：2010-07-22

Applicant: QUALCOMM INC ,  CASSIA MARCO

Inventor： CASSIA MARCO

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K19/00315

Abstract: High voltage logic circuits that can handle digital input and output signals having a larger voltage range are described. In an exemplary design, a high voltage logic circuit includes an input stage, a second stage, and an output stage. The input stage receives at least one input signal and provides (i) at least one first intermediate signal having a first voltage range and (ii) at least one second intermediate signal having a second voltage range. The second stage receives and processes the first and second intermediate signals based on a logic function and provides (i) a first drive signal having the first voltage range and (ii) a second drive signal having the second voltage range. The output stage receives the first and second drive signals and provides an output signal having a third voltage range, which may be larger than each of the first and second voltage ranges.

Abstract translation: 描述了可以处理具有较大电压范围的数字输入和输出信号的高压逻辑电路。 在示例性设计中，高电压逻辑电路包括输入级，第二级和输出级。 输入级接收至少一个输入信号并且提供（i）具有第一电压范围的至少一个第一中间信号和（ii）具有第二电压范围的至少一个第二中间信号。 第二级基于逻辑函数接收并处理第一和第二中间信号，并且提供（i）具有第一电压范围的第一驱动信号和（ii）具有第二电压范围的第二驱动信号。 输出级接收第一和第二驱动信号并提供具有第三电压范围的输出信号，该第三电压范围可以大于第一和第二电压范围中的每一个。

公开(公告)号：WO2010014983A3

公开(公告)日：2010-11-11

申请号：PCT/US2009052578

申请日：2009-08-03

Applicant: QUALCOMM INC ,  TANG YIWU ,  HOLENSTEIN CHRISTIAN ,  CASSIA MARCO ,  RANJAN MAHIM

Inventor： TANG YIWU ,  HOLENSTEIN CHRISTIAN ,  CASSIA MARCO ,  RANJAN MAHIM

IPC: H04L1/06 ,  H04L1/08

CPC classification number: H04B7/0682 ,  H04L1/0618 ,  H04L1/08

Abstract: An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. Both the primary transmit signal path and the diversity transmit signal path may receive a primary transmit signal. A signal selector within the diversity transmit signal path may perform phase rotation with respect to the primary transmit signal while the primary transmit signal is at a baseband frequency, thereby producing a diversity transmit signal.

Abstract translation: 用于实现发射分集的基带频率的相位旋转的设备可以包括主发射信号路径和分集发射信号路径。 主发射信号路径和分集发射信号路径都可以接收主发射信号。 分集发送信号路径内的信号选择器可以在主发送信号处于基带频率时相对于主发送信号执行相位旋转，由此产生分集发送信号。