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    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS
    2.
    发明专利
    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS 未知

    公开(公告)号：CA2717978C

    公开(公告)日：2014-05-27

    申请号：CA2717978

    申请日：2009-03-28

    Applicant: QUALCOMM INC

    Inventor： CHALLA RAGHU N ,  SAMPATH HEMANTH ,  ROSTAMPISHEH ALI

    IPC: H04L1/00

    Abstract: An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memo-ry segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS
    3.
    发明专利
    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS 未知

    公开(公告)号：CA2717978A1

    公开(公告)日：2009-10-01

    申请号：CA2717978

    申请日：2009-03-28

    Applicant: QUALCOMM INC

    Inventor： CHALLA RAGHU N ,  SAMPATH HEMANTH ,  ROSTAMPISHEH ALI

    IPC: H04L1/00

    Abstract: An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

    ZEROING-OUT LLRS USING DEMOD-BITMAP TO IMPROVE PERFORMANCE OF MODEM DECODER
    4.
    发明专利
    ZEROING-OUT LLRS USING DEMOD-BITMAP TO IMPROVE PERFORMANCE OF MODEM DECODER 未知

    公开(公告)号：CA2718135A1

    公开(公告)日：2009-10-01

    申请号：CA2718135

    申请日：2009-03-25

    Applicant: QUALCOMM INC

    Inventor： CHALLA RAGHU N ,  LIN JEREMY H

    IPC: H04L25/06

    Abstract: A demodulation mask bitmap includes binary mask values. Each mask value corresponds to an input resource element to a demodulator. For each mask value of a first state, a demodulation engine of the demodulator is not clocked and the demodulator outputs a zero-valued resource element. For each mask value of a second state, the demodulation engine is clocked, the input resource element is demodulated, and the demodulator outputs a demodulated resource element. A demodulation mask bitmap is designed to mask pilot resource elements and corrupted resource elements. Power is conserved by not clocking the demodulation engine for corrupted and pilot resource elements. Subsequent LLR generation and decode operations are simplified. Decoder performance is improved because the decoder does not decode LLR values derived from corrupted resource elements and/or resource elements not relevant to the reconstruction of a communicated message.

    ZEROING-OUT LLRS USING DEMOD-BITMAP TO IMPROVE PERFORMANCE OF MODEM DECODER
    6.
    发明专利
    ZEROING-OUT LLRS USING DEMOD-BITMAP TO IMPROVE PERFORMANCE OF MODEM DECODER 未知

    公开(公告)号：CA2718135C

    公开(公告)日：2014-10-07

    申请号：CA2718135

    申请日：2009-03-25

    Applicant: QUALCOMM INC

    Inventor： CHALLA RAGHU N ,  LIN JEREMY H

    IPC: H04L25/06

    Abstract: A demodulation mask bitmap includes binary mask values. Each mask value corresponds to an input resource element to a demodulator. For each mask value of a first state, a demodulation engine of the demodulator is not clocked and the demodulator outputs a zero-valued resource element. For each mask value of a second state, the demodulation engine is clocked, the input resource element is demodulated, and the demodulator outputs a demodulated resource element. A demodulation mask bitmap is designed to mask pilot resource elements and corrupted resource elements. Power is conserved by not clocking the demodulation engine for corrupted and pilot resource elements. Subsequent LLR generation and decode operations are simplified. Decoder performance is improved because the decoder does not decode LLR values derived from corrupted resource elements and/or resource elements not relevant to the reconstruction of a communicated message.

    BROADBAND PILOT CHANNEL ESTIMATION USING A REDUCED ORDER FFT AND A HARDWARE INTERPOLATOR
    7.
    发明申请
    BROADBAND PILOT CHANNEL ESTIMATION USING A REDUCED ORDER FFT AND A HARDWARE INTERPOLATOR 审中-公开
    使用减少订单FFT和硬件插入器的宽带导频信道估计

    公开(公告)号：WO2009142804A2

    公开(公告)日：2009-11-26

    申请号：PCT/US2009037438

    申请日：2009-03-17

    Applicant: QUALCOMM INC ,  BUDIANU PETRU CRISTIAN ,  CHAUDHURI ARUNAVA ,  CHALLA RAGHU N

    Inventor： BUDIANU PETRU CRISTIAN ,  CHAUDHURI ARUNAVA ,  CHALLA RAGHU N

    IPC: H04J11/00 ,  H04K1/10

    CPC classification number: H04L25/0202 ,  H04B1/76 ,  H04J11/00 ,  H04L25/0212 ,  H04L25/023 ,  H04L25/0232

    Abstract: Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.

    Abstract translation: 在接收机内，信道估计机制涉及硬件插值器。 在第一模式中，分析窄带导频值以产生提供给内插器的信道参数，使得内插器生成信道估计值。 信道估计值用于解调帧的瓦片。 在第二模式中，宽带导频值被提供给IFFT，从而产生时域值。 在时域处理之后，采用FFT来产生中间信道估计值。 分析这些中间值以确定信道参数，其又被提供给硬件插值器，使得内插器产生更大数量的信道估计值。 相位调整后，信道估计值用于解调。 在宽带模式下使用内插器允许所采用的FFT具有较小的次序，并且消耗更少的功率和/或处理资源。

    HARDWARE ENGINE TO DEMODULATE SIMO, MIMO, AND SDMA SIGNALS
    8.
    发明申请
    HARDWARE ENGINE TO DEMODULATE SIMO, MIMO, AND SDMA SIGNALS 审中-公开
    硬件引擎解密SIMO，MIMO和SDMA信号

    公开(公告)号：WO2009120911A8

    公开(公告)日：2010-10-07

    申请号：PCT/US2009038470

    申请日：2009-03-26

    Applicant: QUALCOMM INC ,  CHALLA RAGHU N ,  SAMPATH HEMANTH ,  BARRIAC GWENDOLYN D

    Inventor： CHALLA RAGHU N ,  SAMPATH HEMANTH ,  BARRIAC GWENDOLYN D

    IPC: H04L25/03

    CPC classification number: H04L25/03019 ,  H04L2025/03426 ,  H04L2025/03726

    Abstract: An apparatus including a configurable demodulation architecture which includes a control module and a demodulation engine. The control module includes a set of one or more control fields. The demodulation engine includes a spatial whitening module, a Minimum Mean Square Estimation (MMSE) module, at least a first Maximal Ratio Combining (MRC) module, and at least one multiplexer. Further, the multiplexer is coupled to the instruction module and controlled based on the control fields to select at least one of the MMSE module or MRC module.

    Abstract translation: 一种包括可配置解调架构的装置，其包括控制模块和解调引擎。 控制模块包括一组一个或多个控制域。 解调引擎包括空间白化模块，最小均方估计（MMSE）模块，至少第一最大比组合（MRC）模块和至少一个多路复用器。 此外，多路复用器耦合到指令模块并且基于控制字段来控制，以选择MMSE模块或MRC模块中的至少一个。

    MULTI-STAGE INTERFERENCE SUPPRESSION
    9.
    发明申请
    MULTI-STAGE INTERFERENCE SUPPRESSION 审中-公开
    多级干扰抑制

    公开(公告)号：WO2011028978A3

    公开(公告)日：2011-04-28

    申请号：PCT/US2010047775

    申请日：2010-09-03

    Applicant: QUALCOMM INC ,  ABRISHAMKAR FARROKH ,  SIKRI DIVAYDEEP ,  CHALLA RAGHU N ,  CANPOLAT BAHADIR

    Inventor： ABRISHAMKAR FARROKH ,  SIKRI DIVAYDEEP ,  CHALLA RAGHU N ,  CANPOLAT BAHADIR

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/0328 ,  H04L25/0202 ,  H04L25/03286 ,  H04L25/03292 ,  H04L25/03299 ,  H04L2025/03726

    Abstract: A multi-stage interference suppression receiver includes a short equalizer section configured to operate on a first portion of a received signal received over a channel to produce a first equalized signal and a first estimate of the channel, a channel estimator section configured to operate on the first equalized signal to produce a second equalized signal, the channel estimator section comprising a linear estimator and a non-linear estimator, a long equalizer section configured to operate on a second portion of the received signal to produce a first estimate of symbols in the received signal and a second estimate of the channel and an interference canceller section configured to operate on the first estimate of symbols in the received signal to generate a second estimate of symbols in the received signal based on, at least in part, the second estimate of the channel.

    Abstract translation: 一种多级干扰抑制接收机，包括：短均衡器部分，被配置为对通过信道接收的接收信号的第一部分进行操作以产生第一均衡信号和信道的第一估计;信道估计器部分，被配置为对 第一均衡信号以产生第二均衡信号，信道估计器部分包括线性估计器和非线性估计器;长均衡器部分，被配置为对接收信号的第二部分进行操作以产生接收到的符号的第一估计 信号和信道的第二估计，以及干扰消除器部分，被配置为对接收信号中的符号的第一估计进行操作，以至少部分地基于第二估计来生成接收信号中的符号的第二估计 渠道。

    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS
    10.
    发明申请
    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS 审中-公开
    构建多个通道的通道

    公开(公告)号：WO2009121045A3

    公开(公告)日：2010-04-08

    申请号：PCT/US2009038705

    申请日：2009-03-28

    Applicant: QUALCOMM INC ,  CHALLA RAGHU N ,  SAMPATH HEMANTH ,  ROSTAMPISHEH ALI

    Inventor： CHALLA RAGHU N ,  SAMPATH HEMANTH ,  ROSTAMPISHEH ALI

    IPC: H04L1/00

    CPC classification number: H04L1/0045 ,  H03M13/2957 ,  H03M13/6566 ,  H04L5/0007 ,  H04L27/2647

    Abstract: An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

    Abstract translation: 描述了一种用于在移动通信系统中增强接收信道的下行链路处理的装置和方法，其包括用于控制数据和业务数据的缓冲器，具有至少两个独立操作的解映射器的解映射器引擎，用于解映射控制和业务数据， 用于支持由解映射器引擎可访问的存储器段的似然比（LLR）缓冲器，包含解码器的解码器引擎，每个解码器对来自所选择的LLR缓冲器的所选存储器段的数据进行操作，以及至少提供至少控制的仲裁器 一个解映射引擎，LLR缓冲区和解码引擎。 解码器中的至少一个适合于解码控制数据，并且解码器中的另一个适合于解码业务数据。 通过分解解码，可以获得下行链路吞吐量的增加。

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