公开(公告)号：AU2002303813A1

公开(公告)日：2002-11-25

申请号：AU2002303813

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： IRVINE A CHRIS ,  LAROCCA JUDITH ,  LEVIN A JEFFREY

IPC: G06F15/00 ,  H03M20060101 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12

Abstract: An apparatus to determine the inverse transform of a block of encoded data the block of encoded data comprising a plurality of compressed frequency domain data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：AU7812001A

公开(公告)日：2002-02-18

申请号：AU7812001

申请日：2001-08-01

Applicant: QUALCOMM INC

Inventor： GOVINDASWAMY SENTHIL ,  IRVINE A CHRIS ,  LEVIN JEFF

IPC: H03M7/40 ,  H03M7/42 ,  H04N7/30

Abstract: An apparatus and method for minimizing the code length of an input address for at least one for variable length encoded data is claimed. A block of variable length encoded data is read. The block of variable length encoded data is then converted into sub-optimall encoded data. The variable length encoded data is defined in having a prefix portion and a suffix portion. The prefix portion of the variable length encoded data is used to signify the look-up table. The suffix portion of the variable length encoded data is used as an input address for the look-up table.

公开(公告)号：CA2791788C

公开(公告)日：2016-05-31

申请号：CA2791788

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE A CHRIS ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  H04N19/60 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50 ,  H04N19/433 ,  H04N19/436 ,  H04N19/625

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：CA2446874C

公开(公告)日：2014-01-28

申请号：CA2446874

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE A CHRIS ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：AR031123A1

公开(公告)日：2003-09-10

申请号：ARP010103773

申请日：2001-08-07

Applicant: QUALCOMM INC

Inventor： GOVINDASWAMY SENTHIL ,  IRVINE A CHRIS ,  LEVIN JEFF

IPC: H03M7/40 ,  H03M7/42 ,  H04N7/30

Abstract: Se reivindica un aparato y método para minimizar la longitud de codigo de una direccion de entrada para por lo menos una tabla de referencia para datos codificados de longitud variable. Se lee un bloque de datos codificados de longitud variable. El bloque de datos codificados de longitud variable luego se convierte a datos codificados sub-optimos.. El dato codificado de longitud variable está definido por tener una porcion de prefijo y una porcion de sufijo. La porcion de sufijo de los datos codificados de longitud variable se utiliza para significar la tabla de referencia. La porcion de sufijo de los datos codificados de longitud variable se utiliza como direccion de entrada para la tabla de referencia.

公开(公告)号：CA2791788A1

公开(公告)日：2002-11-21

申请号：CA2791788

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE A CHRIS ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  H04N7/30 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/50

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：WO02093750A2

公开(公告)日：2002-11-21

申请号：PCT/US0215914

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE A CHRIS ,  LEVIN A JEFFREY

IPC: G06F15/00 ,  H03M20060101 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H03M

CPC classification number: G06F17/147 ,  H04N19/436 ,  H04N19/44 ,  H04N19/625

Abstract: An apparatus to determine the inverse transform of a block of encoded data, the block of encoded data comprising a plurality of compressed frequency domain data elements. An input register (332) is configured to receive a predetermined quantity of data elements. At least one butterfly processor (364) is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register (340) is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

Abstract translation: 一种用于确定编码数据块的逆变换的装置，所述编码数据块包括多个压缩频域数据元素。 输入寄存器（332）被配置为接收预定量的数据元素。 至少一个蝶形处理器（364）耦合到输入寄存器，并且被配置为对所选择的数据元素对执行至少一个数学运算，以产生经处理的数据元素的输出。 至少一个中间寄存器（340）耦合到蝶形处理器并被配置为临时存储处理后的数据。 反馈回路耦合到中间寄存器和蝶形处理器，并且如果启用，则被配置为将经处理的数据元素的第一部分传送到适当的蝶形处理器以执行附加的数学运算，并且如果被禁用则被配置为传送第二 处理的数据元素的一部分到至少一个保持寄存器。